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    Nonvolatile memory device and method for fabricating the same
    4.
    发明授权
    Nonvolatile memory device and method for fabricating the same 有权

    公开(公告)号：US11031410B2

    公开(公告)日：2021-06-08

    申请号：US16425365

    申请日：2019-05-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Se Jun Park ,  Min-Tai Yu ,  Jae Duk Lee

    IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/06

    Abstract: A nonvolatile memory device in which reliability is improved and a method for fabricating the same are provided. The nonvolatile memory device includes a mold structure which includes a first insulating pattern, a first gate electrode and a second insulating pattern sequentially stacked on a substrate, a semiconductor pattern which penetrates the mold structure, is connected to the substrate, and extends in a first direction, a first charge storage film extending in the first direction between the first insulating pattern and the second insulating pattern and between the first gate electrode and the semiconductor pattern, and a blocking insulation film between the first gate electrode and the first charge storage film, wherein a first length at which the first charge storage film extends in the first direction is longer than a second length at which the blocking insulation film extends in the first direction.

    Vertical memory device
    5.
    发明授权
    Vertical memory device 有权

    公开(公告)号：US10192883B2

    公开(公告)日：2019-01-29

    申请号：US15863342

    申请日：2018-01-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Young Hwan Son ,  Young Woo Park ,  Jae Duk Lee

    IPC: H01L27/115 ,  G11C16/04 ,  H01L27/11582 ,  H01L27/11573 ,  G11C16/26 ,  G11C16/10 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575

    Abstract: A memory device may include a peripheral region and a cell region. The peripheral region may include a first substrate, a plurality of circuit elements disposed on the first substrate, a first insulating layer disposed on the plurality of circuit elements, and a first protective layer disposed in the first insulating layer. The cell region may include a second substrate disposed on the first insulating layer, wherein the ceil region includes a first impurity region, a channel region extending in a direction substantially perpendicular to an upper surface of the second substrate, a plurality of gate electrode layers stacked on the second substrate and adjacent to the channel region, and a first contact electrically connected to the first impurity region, wherein the first protective layer is disposed below the first impurity region, and has a shape corresponding to a shape of the first impurity region.

    Semiconductor memory device and storage system including semiconductor memory device
    6.
    发明授权
    Semiconductor memory device and storage system including semiconductor memory device 有权

    公开(公告)号：US12154632B2

    公开(公告)日：2024-11-26

    申请号：US18545144

    申请日：2023-12-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hye Ji Lee ,  Jin-Kyu Kang ,  Rae Young Lee ,  Se Jun Park ,  Jae Duk Lee ,  Gu Yeon Han

    IPC: G11C16/16 ,  G11C11/56 ,  G11C16/04 ,  H10B41/27 ,  H10B43/27

    Abstract: A semiconductor memory device includes a source layer, a channel structure, gate electrodes on the source layer and spaced apart on a sidewall of the channel structure, and a common source line. The gate electrodes include a first word line group including first and second gate electrodes and a second word line group including third and fourth gate electrodes. The semiconductor memory device, in response to a voltage of the common source line reaching a target voltage, causes an inhibition voltage to be applied to the second word line group and an erase voltage to be applied to the first word line group in a first erase operation interval, and causes the inhibition voltage to be applied to the first word line group and the erase voltage to be applied to the second word line group in a second erase operation interval.

    Three-dimensional semiconductor device
    10.
    发明授权
    Three-dimensional semiconductor device 有权

    公开(公告)号：US11574923B2

    公开(公告)日：2023-02-07

    申请号：US17152883

    申请日：2021-01-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jang Gn Yun ,  Jae Duk Lee

    IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524

    Abstract: A three-dimensional semiconductor device includes a stacked structure on a lower structure, the stacked structure including a lower group including gate electrodes vertically stacked and spaced apart from each other, and an upper group including gate electrodes vertically stacked and spaced apart, the lower group and the upper group being vertically stacked, and a vertical structure passing through the stacked structure. The vertical structure may include a vertical core pattern, a vertical buffer portion therein, and a surrounding vertical semiconductor layer, the vertical structure may include a lower vertical portion passing through the lower group and an upper vertical portion passing through the upper group, an upper region of the lower vertical portion may have a width greater than that of a lower region of the upper vertical portion. The vertical buffer portion may be in the lower vertical portion and below the upper vertical portion.

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