Invention Grant
- Patent Title: Semiconductor memory device including vertical insulating pattern including a diffused metal and method of fabricating the same
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Application No.: US17211129Application Date: 2021-03-24
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Publication No.: US12207465B2Publication Date: 2025-01-21
- Inventor: Byung Chul Jang , Sang-Yong Park , Jae Duk Lee
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Suwon-si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si
- Agency: HARNESS, DICKEY & PIERCE, P.L.C.
- Priority: KR10-2020-0087201 20200715
- Main IPC: H10B43/27
- IPC: H10B43/27 ; H10B41/10 ; H10B41/27 ; H10B41/40 ; H10B43/10 ; H10B43/40

Abstract:
A semiconductor memory device includes a stacked structure on a substrate and a vertical structure penetrating the stacked structure. The stacked structured includes a plurality of conductive lines stacked on the substrate. The vertical structure may include a vertical insulating pattern and a channel film extending along sidewalls of the vertical insulating pattern. The vertical insulating pattern may include an inner region and an outer region. The outer region of the vertical insulating pattern may be placed between the channel film and the inner region of the vertical insulating pattern, and the outer region of the vertical insulating pattern may include a diffused metal.
Public/Granted literature
- US20220020766A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME Public/Granted day:2022-01-20
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