公开(公告)号：US12120883B2

公开(公告)日：2024-10-15

申请号：US17666448

申请日：2022-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Yong Park ,  Jin-Hong Park ,  Sungjoo Lee

IPC: H10B51/20 ,  H01L29/51 ,  H01L29/78 ,  H10B51/30

CPC classification number: H10B51/20 ,  H01L29/516 ,  H01L29/78391 ,  H10B51/30

Abstract: A semiconductor memory device capable of improving performance by the use of a charge storage layer including a ferroelectric material is provided. The semiconductor memory device includes a substrate, a tunnel insulating layer contacting the substrate, on the substrate, a charge storage layer contacting the tunnel insulating layer and including a ferroelectric material, on the tunnel insulating layer, a barrier insulating layer contacting the charge storage layer, on the charge storage layer, and a gate electrode contacting the barrier insulating layer, on the barrier insulating layer.

公开(公告)号：USD799440S1

公开(公告)日：2017-10-10

申请号：US29568714

申请日：2016-06-21

Applicant: Samsung Electronics Co., Ltd.

Designer： Jang-Ho Kim ,  Chul-Yong Cho ,  Sang-Yong Park ,  Ki-Hong Kim

公开(公告)号：US20250133738A1

公开(公告)日：2025-04-24

申请号：US18661467

申请日：2024-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chulmin Choi ,  Changhee Lee ,  Dajin Kim ,  Jiwoong Kim ,  Tae Hun Kim ,  Sang-Yong Park ,  Seung Jae Baik ,  Gun-Wook Yoon ,  Jaeduk Lee

IPC: H10B43/27 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: A semiconductor device includes a gate stack with alternating conductive patterns and insulating patterns. The device also includes a first memory channel structure including a first channel layer enclosed by the gate stack and a first memory layer enclosing the first channel layer. The device also includes a source structure electrically connected to the first channel layer. The source structure includes several source layers stacked atop one another. The first channel layer is in physical contact with the second source layer but apart from the other source layers. The first source layer contains impurities of a first conductivity type. The second source layer is formed of an impurity-free material. The third source layer contains impurities of a second conductivity type different from the first conductivity type.

公开(公告)号：US09269722B2

公开(公告)日：2016-02-23

申请号：US14800322

申请日：2015-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Yong Park ,  Jintaek Park

IPC: H01L29/72 ,  H01L27/115 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L21/31144 ,  H01L21/32139 ,  H01L23/5283 ,  H01L27/0207 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11578 ,  H01L29/66833 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional semiconductor device includes a stacked structure including a plurality of conductive layers stacked on a substrate, a distance along a first direction between sidewalls of an upper conductive layer and a lower conductive layer being smaller than a distance along a second direction between sidewalls of the upper conductive layer and the lower conductive layer, the first and second directions crossing each other and defining a plane parallel to a surface supporting the substrate, and vertical channel structures penetrating the stacked structure.

Abstract translation: 三维半导体器件包括堆叠结构，其包括堆叠在衬底上的多个导电层，沿着上导电层的侧壁和下导电层之间的第一方向的距离小于沿着侧壁之间的第二方向的距离 所述第一和第二方向彼此交叉并且限定平行于支撑所述基板的表面的平面，以及穿过所述堆叠结构的垂直通道结构。

公开(公告)号：US12207465B2

公开(公告)日：2025-01-21

申请号：US17211129

申请日：2021-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byung Chul Jang ,  Sang-Yong Park ,  Jae Duk Lee

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

Abstract: A semiconductor memory device includes a stacked structure on a substrate and a vertical structure penetrating the stacked structure. The stacked structured includes a plurality of conductive lines stacked on the substrate. The vertical structure may include a vertical insulating pattern and a channel film extending along sidewalls of the vertical insulating pattern. The vertical insulating pattern may include an inner region and an outer region. The outer region of the vertical insulating pattern may be placed between the channel film and the inner region of the vertical insulating pattern, and the outer region of the vertical insulating pattern may include a diffused metal.

公开(公告)号：US09825053B2

公开(公告)日：2017-11-21

申请号：US15047392

申请日：2016-02-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Yong Park ,  Jintaek Park

IPC: H01L27/11582 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/28 ,  H01L27/02 ,  H01L27/11565 ,  H01L27/11578 ,  H01L29/66 ,  H01L29/792 ,  H01L23/528 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L21/31144 ,  H01L21/32139 ,  H01L23/5283 ,  H01L27/0207 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11578 ,  H01L29/66833 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional semiconductor device includes a stacked structure including a plurality of conductive layers stacked on a substrate, a distance along a first direction between sidewalls of an upper conductive layer and a lower conductive layer being smaller than a distance along a second direction between sidewalls of the upper conductive layer and the lower conductive layer, the first and second directions crossing each other and defining a plane parallel to a surface supporting the substrate, and vertical channel structures penetrating the stacked structure.

公开(公告)号：USD799441S1

公开(公告)日：2017-10-10

申请号：US29569162

申请日：2016-06-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Designer： Sang-Yong Park ,  Chul-Yong Cho ,  Ki-Hong Kim ,  Jang-Ho Kim

公开(公告)号：USD777697S1

公开(公告)日：2017-01-31

申请号：US29567907

申请日：2016-06-14

Applicant: Samsung Electronics Co., Ltd.

Designer： Jang-Ho Kim ,  Chul-Yong Cho ,  Sang-Yong Park ,  Ki-Hong Kim

公开(公告)号：US11925015B2

公开(公告)日：2024-03-05

申请号：US17024987

申请日：2020-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Yong Park ,  Kee-Jeong Rho ,  Hyeong Park ,  Tae-Wan Lim

IPC: H10B12/00 ,  H01L23/31 ,  H01L23/528 ,  H01L29/423 ,  H01L29/78 ,  H01L29/792 ,  H10B43/27 ,  H10B43/30 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50

CPC classification number: H10B12/50 ,  H01L23/3171 ,  H01L23/3185 ,  H01L23/528 ,  H01L29/42352 ,  H01L29/4236 ,  H01L29/7827 ,  H01L29/7926 ,  H10B43/27 ,  H10B43/30 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Vertical memory devices, and methods of manufacturing the same, include providing a substrate including a cell array region and a peripheral circuit region, forming a mold structure in the cell array region, forming an opening for a common source line passing through the mold structure and extending in a first direction perpendicular to a top surface of the substrate, forming a first contact plug having an inner sidewall delimiting a recessed region in the opening for the common source line, and forming a common source bit line contact electrically connected to the inner sidewall of the first contact plug.

公开(公告)号：US11315948B2

公开(公告)日：2022-04-26

申请号：US16939858

申请日：2020-07-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Yong Park ,  Jintaek Park

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/28 ,  H01L27/02 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11578 ,  H01L23/528 ,  H01L27/1157

Abstract: A three-dimensional semiconductor device includes a stacked structure including a plurality of conductive layers stacked on a substrate, a distance along a first direction between sidewalls of an upper conductive layer and a lower conductive layer being smaller than a distance along a second direction between sidewalls of the upper conductive layer and the lower conductive layer, the first and second directions crossing each other and defining a plane parallel to a surface supporting the substrate, and vertical channel structures penetrating the stacked structure.