公开(公告)号：US20180308992A1

公开(公告)日：2018-10-25

申请号：US15944399

申请日：2018-04-03

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： MASAO UCHIDA

IPC: H01L29/872 ,  H01L29/16 ,  H01L29/06 ,  H01L29/66 ,  H01L21/04

CPC classification number: H01L29/872 ,  H01L21/0465 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66068

Abstract: A semiconductor device includes a semiconductor substrate, a silicon carbide semiconductor layer disposed on the semiconductor substrate, and a termination region disposed in the silicon carbide semiconductor layer. The termination region has a guard ring region and an FLR region which is disposed to surround the guard ring region while being separated from the guard ring region, the FLR region including a plurality of rings. The termination region includes a sector section, and in the sector section, an inner circumference and an outer circumference of at least one of the plurality of rings and an inner circumference and an outer circumference of the guard ring region have a same first center of curvature, the first center of curvature being positioned inside the inner circumference of the guard ring region, and a radius of curvature of the inner circumference of the guard ring region is 50 μm or less.

公开(公告)号：US20200266268A1

公开(公告)日：2020-08-20

申请号：US16726982

申请日：2019-12-26

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： MASAO UCHIDA ,  KOUICHI SAITOU ,  TAKASHI HASEGAWA

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/47

Abstract: A semiconductor device includes a silicon carbide semiconductor layer, a termination region disposed in the silicon carbide semiconductor layer, an insulating film covering part of the termination region, an electrode disposed on the silicon carbide semiconductor layer, a seal ring disposed on remaining part of the termination region and surrounding the electrode, and a passivation film covering the insulating film and the seal ring. Assuming that an outer peripheral end of the seal ring and an outer peripheral end of the passivation film have distance L2 at a side of the silicon carbide semiconductor layer, the outer peripheral end of the seal ring and the outer peripheral end of the passivation film have distance L1 at a corner, and the outer peripheral end of the passivation film at the corner has radius of curvature R1, L1>L2 and R1≥L2 are satisfied.

公开(公告)号：US20180174938A1

公开(公告)日：2018-06-21

申请号：US15834035

申请日：2017-12-06

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： MASAO UCHIDA

IPC: H01L23/31 ,  H01L29/16 ,  H01L29/06 ,  H01L23/00

CPC classification number: H01L23/3171 ,  H01L23/3192 ,  H01L23/562 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/1608 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/872

Abstract: Semiconductor device 1000 includes semiconductor 102, an electric field relaxation structure, at least one surface electrode 112, passivation layer 114, and insulating layer 115. Semiconductor layer 102 has a predetermined element region. The electric field alleviation structure is disposed on semiconductor 102 at an end of the element region. On semiconductor 102, surface electrode 112 is disposed inside the electric field alleviation structure when viewed in a normal direction of semiconductor 102. Passivation layer 114 covers the electric field alleviation structure and a peripheral portion of at least one surface electrode 112, and has an opening portion above surface electrode 112. On surface electrode 112, insulating layer 115 is disposed inside opening portion 114p so as to be separated from passivation layer 114. When viewed in the normal direction of semiconductor 102, insulating layer 115 is disposed so as to surround partial region 112a of surface electrode 112.

公开(公告)号：US20190244879A1

公开(公告)日：2019-08-08

申请号：US16255874

申请日：2019-01-24

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： ATSUSHI OHOKA ,  NOBUYUKI HORIKAWA ,  MASAO UCHIDA

IPC: H01L23/482 ,  H01L29/16 ,  H01L29/06 ,  H01L29/78

Abstract: A silicon carbide semiconductor device includes an upper gate electrode including a gate pad and a gate wiring line, and an upper source electrode including first and second source pads. The gate wiring line includes a gate global wiring line extending to encircle the source pads, and a gate connection wiring line. The upper source electrode includes an outer periphery source wiring line extending to encircle the gate global wiring line, and first and second source connections connecting the outer periphery source wiring line to the first and second source pads, respectively. The gate global wiring line includes a first portion, a second portion, and a third portion. The first portion is split at a first substrate corner and a second substrate corner and lies between the first substrate corner and the second substrate corner.splitsplit

公开(公告)号：US20170098647A1

公开(公告)日：2017-04-06

申请号：US15251886

申请日：2016-08-30

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： MASAO UCHIDA ,  NOBUYUKI HORIKAWA

IPC: H01L27/06 ,  H01L29/78 ,  H01L29/16

CPC classification number: H01L27/0629 ,  H01L21/8213 ,  H01L27/0605 ,  H01L27/0727 ,  H01L29/1608 ,  H01L29/7827

Abstract: A semiconductor device includes a first silicon carbide semiconductor layer, a source including a source pad and a source wiring, a gate including a gate pad and a gate wiring, first unit cells disposed in a first element region, and second unit cells disposed in a second element region. In a plan view, the first and second element regions are adjacent to each other with the gate wiring between the first and second element regions. A first electrode including the gate electrode of each first unit cell is disposed in the first element region and electrically connected to the gate. A second electrode including the gate electrode of each second unit cell is disposed in the second element region and not electrically connected to the gate. The first and second electrodes are separated below the gate wiring.

公开(公告)号：US20190245052A1

公开(公告)日：2019-08-08

申请号：US16255875

申请日：2019-01-24

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： ATSUSHI OHOKA ,  NOBUYUKI HORIKAWA ,  MASAO UCHIDA

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/10 ,  H01L29/417 ,  H01L23/528

Abstract: The silicon carbide semiconductor device includes a plurality of unit cells each having an MISFET structure and provided on a silicon carbide semiconductor substrate. A gate upper electrode disposed adjacent to the plurality of unit cells includes a gate pad and gate global wires. When viewed in plan, gate electrodes do not overlap with the gate pad.

公开(公告)号：US20190245043A1

公开(公告)日：2019-08-08

申请号：US16260721

申请日：2019-01-29

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： MASAO UCHIDA

IPC: H01L29/16 ,  H01L29/06 ,  H01L29/24 ,  H01L29/66 ,  H01L29/872 ,  H01L29/08

CPC classification number: H01L29/1608 ,  H01L29/0619 ,  H01L29/08 ,  H01L29/24 ,  H01L29/66143 ,  H01L29/66212 ,  H01L29/66969 ,  H01L29/872

Abstract: A semiconductor element includes: a semiconductor substrate of a first conduction type; a silicon carbide semiconductor layer of the first conduction type disposed above a principal surface of the semiconductor substrate; a terminal edge region of a second conduction type disposed in the silicon carbide semiconductor layer; an insulating film; a first electrode disposed on the silicon carbide semiconductor layer; and a seal ring surrounding the first electrode. The terminal edge region is disposed to surround part of a surface of the silicon carbide semiconductor layer when viewed in a normal direction of the principal surface of the semiconductor substrate. The terminal edge region includes a guard ring region of the second conduction type, and a terminal edge injection region of the second conduction type. The seal ring is formed on the terminal edge injection region through an opening disposed on the insulating film.

公开(公告)号：US20170077087A1

公开(公告)日：2017-03-16

申请号：US15342023

申请日：2016-11-02

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： NOBUYUKI HORIKAWA ,  OSAMU KUSUMOTO ,  MASASHI HAYASHI ,  MASAO UCHIDA

IPC: H01L27/06 ,  H01L29/41 ,  H01L29/868 ,  H01L29/06 ,  H01L29/16 ,  H01L29/78

CPC classification number: H01L27/0605 ,  H01L27/04 ,  H01L27/0727 ,  H01L29/06 ,  H01L29/0623 ,  H01L29/12 ,  H01L29/1608 ,  H01L29/41 ,  H01L29/78 ,  H01L29/861 ,  H01L29/8611 ,  H01L29/868

Abstract: A silicon carbide semiconductor device includes a transistor region, a diode region, a gate line region, and a gate pad region. The gate pad region and the gate line region are each disposed to be sandwiched between the diode region and the diode region, and a gate electrode on the gate pad region and the gate line region is formed on an insulating film formed on an epitaxial layer. Thus, breakdown of the insulating film in the gate region can be prevented without causing deterioration in quality of the gate insulating film, upon switching and avalanche breakdown.

Abstract translation: 碳化硅半导体器件包括晶体管区域，二极管区域，栅极线区域和栅极焊盘区域。 栅极区域和栅极线区域分别被设置为夹在二极管区域和二极管区域之间，并且栅极区域上的栅极电极和栅极线区域形成在形成在外延层上的绝缘膜上。 因此，能够防止栅极绝缘膜在开关和雪崩击穿时的栅极区域的绝缘膜的破坏，而不会导致栅极绝缘膜的质量劣化。

公开(公告)号：US20150255544A1

公开(公告)日：2015-09-10

申请号：US14632895

申请日：2015-02-26

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： MASAO UCHIDA ,  MASASHI HAYASHI ,  KOUTAROU TANAKA

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/10 ,  H01L21/04 ,  H01L29/872 ,  H01L29/47 ,  H01L29/45 ,  H01L21/02 ,  H01L29/812 ,  H01L29/36

CPC classification number: H01L29/1608 ,  H01L21/0485 ,  H01L21/0495 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/423 ,  H01L29/45 ,  H01L29/47 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7828 ,  H01L29/872

Abstract: A semiconductor device includes first and second second-conductivity-type region groups containing multiple second-conductivity-type regions that are disposed on a first silicon carbide semiconductor layer of a first conductivity type, arrayed in parallel following one direction with a space between each other, and first and second electrodes disposed on the first silicon carbide semiconductor layer and forming a Schottky junction with the first silicon carbide semiconductor layer. The first electrode covers a position where a distance from adjacent first and second second-conductivity-type regions included in a first second-conductivity-type region group, and a distance from a third second-conductivity-type region included in a second second-conductivity-type region group and adjacent to the first and second second-conductivity-type regions, are equal. A Schottky barrier between the first electrode and the first silicon carbide semiconductor layer is larger than a Schottky barrier between the second electrode and the first silicon carbide semiconductor layer.

Abstract translation: 半导体器件包括第一和第二第二导电型区域组，其包含多个第二导电类型区域，所述第二导电类型区域设置在第一导电类型的第一碳化硅半导体层上，并排沿着一个方向并排放置 以及设置在第一碳化硅半导体层上并与第一碳化硅半导体层形成肖特基结的第一和第二电极。 第一电极覆盖从包括在第一第二导电类型区域组中的相邻第一和第二第二导电类型区域到与包括在第二第二导电类型区域组中的第三第二导电类型区域的距离的位置， 导电类型区域组并且与第一和第二第二导电类型区域相邻。 第一电极和第一碳化硅半导体层之间的肖特基势垒大于第二电极和第一碳化硅半导体层之间的肖特基势垒。

公开(公告)号：US20170317173A1

公开(公告)日：2017-11-02

申请号：US15477186

申请日：2017-04-03

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： MASAO UCHIDA

IPC: H01L29/16 ,  H01L29/73 ,  H01L21/02 ,  H01L31/02 ,  H01L29/66

CPC classification number: H01L29/1608 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/02378 ,  H01L21/02447 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/6606 ,  H01L29/66113 ,  H01L29/7313 ,  H01L29/872 ,  H01L31/02027 ,  H01L31/108

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, having a first principal surface and a second principal surface, a silicon carbide semiconductor layer of the first conductivity type, disposed on the first principal surface, a first electrode disposed on the silicon carbide semiconductor layer, and a second electrode disposed on the second principal surface and forming an ohmic junction with the semiconductor substrate. The semiconductor device satisfies 0.13≦Rc/Rd, where Rc is the contact resistance between the second principal surface and the second electrode at room temperature and Rd is the resistance of the silicon carbide semiconductor layer in a direction normal to the first principal surface at room temperature.