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公开(公告)号：US20250062280A1
公开(公告)日：2025-02-20
申请号：US18234603
申请日：2023-08-16
Applicant: General Electric Company
Inventor： Ljubisa D. Stevanovic , Arun Virupaksha Gowda , Christopher James Kapusta , Risto Ilkka Sakari Tuominen
IPC: H01L25/065 , H01L21/48 , H01L23/00 , H01L23/48
Abstract: A multi-chip semiconductor package includes a dielectric interconnect layer having an upper surface and a bottom surface, at least one common source pad disposed on the upper surface of the interconnect layer, at least one common gate pad disposed on the upper surface of the interconnect layer, and a plurality of semiconductor devices each including a gate pad and at least one source pad adhered onto the interconnect layer, wherein the source pads of the plurality of semiconductor devices are electrically connected to the at least one common source pad, and wherein the source pads of the plurality of semiconductor devices are electrically connected in parallel with one another, and wherein the gate pads of the plurality of semiconductor devices are electrically connected to the common gate pad, and wherein the gate pads of the plurality of semiconductor devices are electrically connected in parallel with one another.
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公开(公告)号：US11982645B2
公开(公告)日：2024-05-14
申请号：US18134788
申请日：2023-04-14
Applicant: General Electric Company
CPC classification number: G01N29/223 , G01D11/245 , G01K11/265 , G01N29/2443 , G01N29/2462
Abstract: A system includes a sensor comprising a sensor bonding layer disposed on a surface of the sensor, wherein the sensor bonding layer is a metallic alloy. An inlay includes a planar outer surface, wherein the inlay may be disposed on a curved surface of a structure. A structure bonding layer may be disposed on the planar outer surface of the inlay, wherein the structure bonding layer is a metallic alloy. The sensor bonding layer is coupled to the structure bonding layer via a metallic joint, and the sensor is configured to sense data of the structure through the metallic joint, the structure bonding layer, and the sensor bonding layer. The inlay comprises at least one of a modulus of elasticity, a shape, a thickness, and a size configured to reduce strain transmitted to the sensor.
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公开(公告)号：US11309304B2
公开(公告)日：2022-04-19
申请号：US15956231
申请日：2018-04-18
Applicant: General Electric Company
Inventor： James Sabatini , Christopher James Kapusta , Glenn Forman
IPC: H01L25/00 , H01L23/538 , H01L23/00 , H01L25/065 , H01L25/16
Abstract: An electronic package includes a first layer having a first surface, the first layer includes a first device having a first electrical node, and a first contact pad in electrical communication with the first electrical node and positioned within the first surface. The package includes a second layer having a second surface and a third surface, the second layer includes a first conductor positioned within the second surface and a second contact pad positioned within the third surface and in electrical communication with the first conductor. A first anisotropic conducting paste (ACP) is positioned between the first contact pad and the first conductor to electrically connect the first contact pad to the first conductor such that an electrical signal may pass therebetween.
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4.发明申请公开(公告)号：US20210204397A1
公开(公告)日：2021-07-01
申请号：US16730435
申请日：2019-12-30
Applicant: General Electric Company
Abstract: An electronics package is disclosed. The electronics package includes a first radio frequency (RF) substrate layer, a second RF substrate layer, and a plurality of conductive layers disposed adjacent to at least one of the first RF substrate layer and the second RF substrate layer and including an inner conductive layer disposed between and adjacent to both the first RF substrate layer and the second RF substrate layer. The inner conductive layer bonds the first RF substrate layer to the second RF substrate layer. The electronics package also includes a plurality of conductive interconnects extending through the first RF substrate layer and the second RF substrate layer and electrically coupled between at least two of the plurality of conductive layers.
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5.发明授权公开(公告)号：US10892237B2
公开(公告)日：2021-01-12
申请号：US16221033
申请日：2018-12-14
Applicant: General Electric Company
Inventor： Stephen Daley Arthur , Liangchun Yu , Nancy Cecelia Stoffel , David Richard Esler , Christopher James Kapusta
Abstract: Methods of fabricating a semiconductor device are provided. The method includes providing a plurality of semiconductor devices. The method further includes disposing a dielectric dry film on the plurality of semiconductor devices, wherein the dielectric dry film is patterned such that openings in the patterned dielectric dry film are aligned with conductive pads of each of the plurality of semiconductor devices.
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Patent Agency Ranking
6.发明授权公开(公告)号：US10804116B2
公开(公告)日：2020-10-13
申请号：US16667018
申请日：2019-10-29
Applicant: General Electric Company
Inventor： Christopher James Kapusta , Raymond Albert Fillion , Risto Ilkka Sakari Tuominen , Kaustubh Ravindra Nagarkar
IPC: H01L21/48 , H01L21/56 , H01L21/52 , H01L23/28 , H01L23/31 , H01L23/14 , H01L23/00 , H01L23/367 , H01L27/14 , H01L27/146 , H01L23/42
Abstract: An electronics package includes an insulating substrate, an electrical component having a back surface coupled to a first surface of the insulating substrate, and an insulating structure surrounding at least a portion of a perimeter of the electrical component. A first wiring layer extends from the first surface of the insulating substrate and over a sloped side surface of the insulating structure to electrically couple with at least one contact pad on an active surface of the electrical component. A second wiring layer is formed on a second surface of the insulating substrate and extends through at least one via therein to electrically couple with the first wiring layer.
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公开(公告)号：US10784576B2
公开(公告)日：2020-09-22
申请号：US15782991
申请日：2017-10-13
Applicant: General Electric Company
Inventor： Joseph Alfred Iannotti , Christopher James Kapusta
Abstract: A beam former module includes a package base and an interconnect structure formed within the package base. The beam former module also includes a first true time delay (TTD) module attached to the package base. The first TTD module includes a plurality of switching elements configured to define a signal transmission path between a signal input and a signal output of the first TTD module by selectively activating a plurality of time delay lines. The signal input and the signal output of the first TTD module are electrically coupled to the interconnect structure. In some embodiments, the interconnect structure includes at least one TTD meander line and at least one of the time delay lines of the first TTD module is electrically coupled to the at least one TTD meander line.
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8.发明授权公开(公告)号：US10770382B2
公开(公告)日：2020-09-08
申请号：US16203777
申请日：2018-11-29
Applicant: General Electric Company
Inventor： Christopher James Kapusta , Ramanujam Ramabhadran , Kum-Kang Huh , Brian Lynn Rowden , Glenn Scott Claydon , Ahmed Elasser
IPC: H01L23/498 , H01L23/64 , H01L23/538 , H01L23/00 , H01L29/20 , H01L21/56
Abstract: A modular electronics package is disclosed that includes a first and second electronics packages, with each of the first and second electronics packages including a metallized insulating substrate and a solid-state switching device positioned on the metallized insulating substrate, the solid-state switching device comprising a plurality of contact pads electrically coupled to the first conductor layer of the metallized insulating substrate. A conductive joining material is positioned between the first electronics package and the second electronics package to electrically connect them together. The first electronics package and the second electronics package are stacked with one another to form a half-bridge unit cell, with the half-bridge unit cell having a current path through the solid-state switching device in the first electronics package and a close coupled return current path through the solid-state switching device in the second electronics package in opposite flow directions.
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公开(公告)号：US10432168B2
公开(公告)日：2019-10-01
申请号：US14841314
申请日：2015-08-31
Applicant: GENERAL ELECTRIC COMPANY
Inventor： Christopher James Kapusta , Marco Francesco Aimi
Abstract: In one embodiment, a bonded quartz wafer package includes a first quartz wafer including at least one quartz-based device, a second quartz wafer disposed above the first quartz wafer, and a liquid crystal polymer (LCP) bonding layer disposed in between the first and second quartz wafers that bonds the first and second quartz wafers together.
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10.发明申请公开(公告)号：US20190043802A1
公开(公告)日：2019-02-07
申请号：US15670423
申请日：2017-08-07
Applicant: General Electric Company
Inventor： Christopher James Kapusta , Raymond Albert Fillion , Risto Ilkka Sakari Tuominen , Kaustubh Ravindra Nagarkar
IPC: H01L23/522 , H01L23/495 , H01L25/04 , H01L23/00 , H01L21/48
CPC classification number: H01L23/5226 , H01L21/486 , H01L23/13 , H01L23/4952 , H01L23/49541 , H01L23/5389 , H01L24/03 , H01L24/82 , H01L24/97 , H01L25/043 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H05K2201/10674 , H01L2924/00012 , H01L2224/45099
Abstract: A method of manufacturing a multi-layer electronics package includes attaching a base insulating substrate to a frame having an opening therein and such that the frame is positioned above and/or below the base insulating substrate to provide support thereto. A first conductive wiring layer is applied on the first side of the base insulating substrate, and vias are formed in the base insulating substrate. A second conductive wiring layer is formed on the second side of the base insulating substrate that covers the vias and the exposed portions of the first conductive wiring layer and at least one additional insulating substrate is bonded to the base insulating substrate. Vias are formed in each additional insulating substrate and an additional conductive wiring layer is formed on each of the additional insulating substrate. The described build-up forms a multilayer interconnect structure, with the frame providing support for this build-up.
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