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公开(公告)号：US20240283433A1
公开(公告)日：2024-08-22
申请号：US18171413
申请日：2023-02-20
发明人： Vishnu RAVINUTHULA , Tianyu Chang
CPC分类号： H03K3/0315 , H03K3/014 , H03K5/135
摘要： An oscillator circuit includes a ring oscillator and a ramp generator. The ring oscillator includes a first inverter and a second inverter. The first inverter has and a first inverter input, a first inverter output, and a first power terminal. The second inverter has a second inverter input, a second inverter output, and a second power terminal. The second inverter input is coupled to the first inverter output and the second inverter output is coupled to the first inverter input. The ramp generator circuit has a ramp output coupled to the first power terminal and the second power terminal.
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公开(公告)号：US12044732B2
公开(公告)日：2024-07-23
申请号：US17494614
申请日：2021-10-05
申请人： NVIDIA Corporation
IPC分类号： G01R31/3183 , G01R31/28 , G01R31/317 , H03K3/03 , H03L7/099
CPC分类号： G01R31/318328 , G01R31/2824 , G01R31/31725 , H03K3/0315 , H03L7/0995
摘要： Silicon test structures are described that enable separate measurement of n-channel metal-oxide semiconductor (NMOS) and p-channel metal-oxide semiconductor (PMOS) transistor delays. NMOS and PMOS specific non-inverting stages may be used to construct a multi-stage ring oscillator. Each of the non-inverting stages generates either a rising or falling primary transition that is determined by either NMOS or PMOS transistors, respectively. The opposing transition for a particular non-inverting stage is triggered by propagation of the primary transition to a subsequent non-inverting stage (producing a “reset” pulse). A frequency of the ring oscillator is determined by the primary transition and one transistor type (NMOS or PMOS). Specifically, the frequency is determined by the propagation delay of the primary transition through the entire ring oscillator.
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3.发明公开公开(公告)号：US20240204758A1
公开(公告)日：2024-06-20
申请号：US18503241
申请日：2023-11-07
发明人： Oskar KRENEK , Christoph KURATLI
CPC分类号： H03K3/0315 , H03K3/01
摘要： A system with a low-drift on-chip (LD-RC) oscillator with lowered sensitivity to Random Telegraph Noise when generating a current (Id) for the LD-RC oscillator. A control resistor (R) is connected through an intermediary arrangement to one of a first MOS transistor (M1) or of a second MOS transistor (M2) between two terminals of a supply voltage source (Vdd). The gate of the first MOS transistor (M1) is connected to the gate of the second MOS transistor (M2), whereas the source of the first MOS transistor (M1) and the source of the second MOS transistor (M2) are connected to one terminal of the supply voltage source (Vdd), the control resistor (R) being connected to the other opposite terminal of the supply voltage source.
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公开(公告)号：US20240171160A1
公开(公告)日：2024-05-23
申请号：US18165350
申请日：2023-02-07
CPC分类号： H03K3/354 , H03K3/0315
摘要： A sensing circuit coupled to a sensor includes a first transistor, a second transistor, a third transistor, a fourth transistor, and an oscillator. The first transistor, coupled to a first current source and the sensor, receives a sensing current from the sensor. A gate terminal of the first transistor is connected to a source terminal of the first transistor. The second transistor, coupled to the first transistor and a second current source, generates a first current according to the sensing current. The first current is greater than the sensing current. The third transistor, coupled to the second transistor and the second current source, generates a second current according to the first current. The fourth transistor, coupled to the third transistor, generates a third current. The oscillator is coupled to the fourth transistor. The oscillator generates a signal having an oscillation frequency according to the third current.
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5.发明授权公开(公告)号：US11990908B1
公开(公告)日：2024-05-21
申请号：US16807979
申请日：2020-03-03
申请人： SiTime Corporation
CPC分类号： H03K3/0315 , G01K7/32 , H03L1/027 , H03L7/0991 , H03L7/18 , H03L7/1976
摘要： In a high resolution temperature sensor, first and second MEMS resonators generate respective first and second clock signals and a locked-loop reference clock generator generates a reference clock signal having a frequency that is phase-locked to at least one of the first and second clock signals. A frequency-ratio engine within the MEMS temperature sensor oversamples at least one of the first and second clock signals with the reference clock signal to generate a ratio of the frequencies of the first and second clock signals.
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公开(公告)号：US11990907B2
公开(公告)日：2024-05-21
申请号：US17954126
申请日：2022-09-27
IPC分类号： H03K3/0231 , H03B5/04 , H03B5/24 , H03K3/03 , H03L7/099
CPC分类号： H03K3/0231 , H03B5/04 , H03B5/24 , H03K3/0315 , H03L7/0992 , H03L7/0995
摘要： One or more devices, systems, and/or methods are provided. In an example of the techniques presented herein, an oscillator comprises a voltage controlled oscillator configured to generate an output clock based on a drive signal, a frequency to voltage converter having a time constant and configured to generate a feedback voltage having a decay cycle based on the time constant and a frequency based on a frequency of the output clock, and an integrator configured to generate the drive signal based on an integration of the feedback voltage and a reference voltage.
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公开(公告)号：US11923853B2
公开(公告)日：2024-03-05
申请号：US17680763
申请日：2022-02-25
申请人： NVIDIA Corp.
发明人： Tezaswi Raja , Prashant Singh
CPC分类号： H03K3/037 , H03K3/0315 , H03K5/01 , H03K2005/00078
摘要： A ring oscillator circuit with a frequency that is sensitive to the timing of a clock-to-Q (clk2Q) propagation delay of one or more flip-flops utilized in the ring oscillator. The clock2Q is the delay between the clock signal arriving at the clock pin on the flop and the Q output reflecting the state of the input data signal to the flop. Clk2q delay measurements are made based on measurement of the ring oscillator frequency, leading to more accurate estimates of clk2Q for different types of flip-flops and flip-flop combinations, which may in turn enable improvements in circuit layouts, performance, and area.
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公开(公告)号：US20240022255A1
公开(公告)日：2024-01-18
申请号：US18358851
申请日：2023-07-25
发明人： Min-Shueh YUAN , Chao-Chieh LI , Chia-Chun LIAO , Yu-Tso LIN , Wen-Yuan TSAI , Chih-Hsien CHANG
CPC分类号： H03L7/0991 , H03H17/0294 , H03L7/107 , H03L7/0995 , H03K3/0322
摘要： An integrated circuit device includes a digitally controlled oscillator (DCO), two charge-sharing capacitors, two charge-sharing switches, two pre-charge switches, and two DACs. The DCO has a first inverter and a second inverter. A first charge-sharing capacitor has a first terminal coupled to an input terminal of the first inverter through a first charge-sharing switch. A first DAC has an output terminal coupled to the first terminal of the first charge-sharing capacitor through a first pre-charge switch. A second charge-sharing capacitor has a first terminal coupled to an input terminal or an output terminal of the second inverter through a second charge-sharing switch. A second DAC has an output terminal coupled to the first terminal of the second charge-sharing capacitor through a second pre-charge switch.
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公开(公告)号：US11876057B1
公开(公告)日：2024-01-16
申请号：US18150942
申请日：2023-01-06
CPC分类号： H01L23/576 , H01L29/0843 , H01L29/78 , H03K3/0315 , H10B10/12
摘要： Systems, methods, circuits, and devices for providing and using transistors in a physically unclonable function (PUF) circuit. The transistors comprise a split source drain configuration including one or more inflection segments that increase process variations between the transistors such that each transistor generates a unique output signal.
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公开(公告)号：US20240014809A1
公开(公告)日：2024-01-11
申请号：US18345726
申请日：2023-06-30
IPC分类号： H03K3/03 , H03K5/1252
CPC分类号： H03K3/0315 , H03K5/1252
摘要： A clock generator circuit includes an oscillator circuit coupled to a bias circuit. The bias circuit includes a current mirror, third and fourth transistors, and a cascode transistor. The current mirror includes a reference transistor and a set of copy transistors that are programmable. The third transistor has a source connected to a cold spot, a drain and a gate connected to this drain. The fourth transistor has a source connected to the drain of the third transistor, a drain, and a gate connected to that drain. The cascode transistor has a source connected to a drain of at least one of the copy transistors, a drain, and a gate connected to the gate of the fourth transistor. The gates of the fourth transistor and the cascode transistor are thicker than the gates of the reference transistor, each copy transistor, and the third transistor.
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