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公开(公告)号：US20230387897A1
公开(公告)日：2023-11-30
申请号：US17828834
申请日：2022-05-31
发明人： Tsung-Che LU , Chin-Ming FU , Chih-Hsien CHANG
CPC分类号： H03K5/01 , H03K3/037 , H03K19/20 , G06F1/06 , H03K2005/00013
摘要： A system includes a measuring device, a processing device and a signal generating device. The measuring device is configured to measure a voltage difference between a first node and a second node. The processing device is coupled between the first node and the second node. The signal generating device is configured to provide a first clock signal to the processing device to adjust the voltage difference, configured to generate the first clock signal according to a first enable signal and a second clock signal, and configured to align an edge of the first enable signal with an edge of the second clock signal. A method and a device are also disclosed herein.
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公开(公告)号：US20220294460A1
公开(公告)日：2022-09-15
申请号：US17829044
申请日：2022-05-31
发明人： Mao-Hsuan CHOU , Chih-Hsien CHANG , Ruey-Bin SHEEN
IPC分类号： H03L7/099
摘要： A counter signal counting at a frequency of a clock signal is generated. Among a plurality of different numeric ranges corresponding to a plurality of different thresholds, a threshold corresponding to a numeric range containing a frequency ratio is selected. In response to the counter signal reaching the selected threshold, a logic level of an output signal is switched.
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公开(公告)号：US20220131534A1
公开(公告)日：2022-04-28
申请号：US17570705
申请日：2022-01-07
IPC分类号： H03K3/03
摘要： A controlling circuit for ring oscillator is provided. A first transistor and a second transistor of a first conductive type are coupled in series and between a node and a first power source. A third transistor and a fourth transistor of a second conductive type are coupled in parallel and between the node and a second power source. The node is coupled to an input of a delay chain of the ring oscillator. The second and third transistors are coupled in series. Gates of the second and third transistors are configured to receive an output signal of the delay chain. When the first transistor is turned off and the fourth transistor is turned on, the node is pulled to a first logic level from a second logic level in order to align a phase of a waveform of the ring oscillator.
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公开(公告)号：US20210028789A1
公开(公告)日：2021-01-28
申请号：US17069237
申请日：2020-10-13
摘要： Phase-locked loops (PLLs) are provided. A PLL includes a voltage-controlled oscillator (VCO), a frequency divider and a track-and-hold charge pump. The VCO is configured to provide an output clock corresponding to a pumping current. The frequency divider is configured to provide a feedback signal according to the output clock. The track-and-hold charge pump is configured to provide the pumping current according to a reference clock and the feedback signal. The track-and-hold charge pump includes a track-and-hold circuit, a pumping switch and a pulse width modulator (PWM). The track-and-hold circuit is coupled to the frequency divider and configured to sample the feedback signal according to the reference clock. The PWM is configured to provide a PWM signal to control the pumping switch according to the reference clock, so as to provide the pumping current corresponding to the sampled feedback signal.
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公开(公告)号：US20230395100A1
公开(公告)日：2023-12-07
申请号：US17805026
申请日：2022-06-01
发明人： Tsung-Che LU , Chin-Ming FU , Chih-Hsien CHANG
CPC分类号： G11C7/062 , G11C7/14 , G11C7/1066 , G11C7/1093 , G11C5/14
摘要： A sense amplifier includes a first pair of transistors having gate terminals respectively coupled to a first input terminal for receiving a first input signal and to a second input terminal for receiving a second input signal, source terminals coupled to a first power supply terminal, and drain terminals. The sense amplifier also includes a second pair of transistors having gate terminals coupled to a clock terminal, source terminals respectively coupled to the drain terminals of the first pair of transistors, and drain terminals. The sense amplifier also includes a third pair of transistors having gate terminals coupled to the clock terminal, drain terminals respectively coupled to the drain terminals of the second pair of transistors, and source terminals coupled to a second power supply terminal. In addition, the sense amplifier includes an output circuit coupled to the drain terminals of the second pair of transistors and having an output terminal.
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公开(公告)号：US20210335991A1
公开(公告)日：2021-10-28
申请号：US17167624
申请日：2021-02-04
IPC分类号： H01L49/02 , H01L23/64 , G06F30/392
摘要： An IC structure includes a resistor circuit and a transistor. The resistor circuit includes a first metal resistor strip over a semiconductor substrate, and a first metal line and a second metal line extending on a same level height above the first metal resistor strip. The first metal resistor strip is a dummy gate. Both the first metal line and the second metal line overlap and are electrically connected to the first metal resistor strip. The transistor includes a metal gate strip on a same level height as the first metal strip and extends in parallel with the first metal resistor strip.
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公开(公告)号：US20210028772A1
公开(公告)日：2021-01-28
申请号：US17065593
申请日：2020-10-08
IPC分类号： H03K3/03
摘要： A controlling circuit for ring oscillator is provided. First and second transistors of a first conductive type are coupled in series and between a node and a first power source. Third and fourth transistors of a second conductive type are coupled in parallel and between the node and a second power source. The node is coupled to an input of a delay chain of the ring oscillator. The second and third transistors are coupled in series and gates of the second and third transistors are configured to receive an output signal of the delay chain. When the first transistor is turned off and the fourth transistor is turned on, the node is pulled to a first logic level from a second logic level in order to align a phase of a waveform of the ring oscillator.
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8.发明申请PHASE LOCK LOOP, VOLTAGE CONTROLLED OSCILLATOR OF THE PHASE LOCK LOOP, AND METHOD OF OPERATING THE VOLTAGE CONTROLLED OSCILLATOR 有权相位锁定环路，相位锁定环路的电压控制振荡器和操作电压控制振荡器的方法公开(公告)号：US20150130522A1
公开(公告)日：2015-05-14
申请号：US14605409
申请日：2015-01-26
发明人： Matt LI , Min-Shueh YUAN , Chih-Hsien CHANG
CPC分类号： H03L1/00 , H03B5/10 , H03L7/06 , H03L7/099 , H03L7/0992
摘要： A voltage controlled oscillator (VCO) includes a sensing circuit, where the sensing circuit is configured to generate a plurality of compensation control signals. The VCO further includes a voltage-to-current converter comprising a plurality of current sources which are configured to generate a current signal in response to the plurality of compensation control signals. Additionally, the VCO includes a plurality of switching circuits, each of the plurality of switching circuits being configured to selectively enable or disable a corresponding one of the plurality of current sources in response to a corresponding one of the plurality of compensation control signals. Furthermore, the VCO includes a current controlled oscillator configured to generate an oscillating signal in response to the current signal.
摘要翻译： 压控振荡器（VCO）包括感测电路，其中感测电路被配置为产生多个补偿控制信号。 VCO还包括电压 - 电流转换器，其包括多个电流源，其被配置为响应于多个补偿控制信号而产生电流信号。 另外，VCO包括多个开关电路，所述多个开关电路中的每一个被配置为响应于所述多个补偿控制信号中的相应一个来选择性地启用或禁用所述多个电流源中的对应的一个。 此外，VCO包括配置为响应于当前信号产生振荡信号的电流控制振荡器。
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公开(公告)号：US20240212723A1
公开(公告)日：2024-06-27
申请号：US18597860
申请日：2024-03-06
发明人： Tsung-Che LU , Chin-Ming FU , Chih-Hsien CHANG
CPC分类号： G11C7/062 , G11C5/14 , G11C7/1066 , G11C7/1093 , G11C7/14
摘要： A sense amplifier includes a first pair of transistors having gate terminals respectively coupled to a first input terminal for receiving a first input signal and to a second input terminal for receiving a second input signal, source terminals coupled to a first power supply terminal, and drain terminals. The sense amplifier also includes a second pair of transistors having gate terminals coupled to a clock terminal, source terminals respectively coupled to the drain terminals of the first pair of transistors, and drain terminals. The sense amplifier also includes a third pair of transistors having gate terminals coupled to the clock terminal, drain terminals respectively coupled to the drain terminals of the second pair of transistors, and source terminals coupled to a second power supply terminal. In addition, the sense amplifier includes an output circuit coupled to the drain terminals of the second pair of transistors and having an output terminal.
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公开(公告)号：US20240022255A1
公开(公告)日：2024-01-18
申请号：US18358851
申请日：2023-07-25
发明人： Min-Shueh YUAN , Chao-Chieh LI , Chia-Chun LIAO , Yu-Tso LIN , Wen-Yuan TSAI , Chih-Hsien CHANG
CPC分类号： H03L7/0991 , H03H17/0294 , H03L7/107 , H03L7/0995 , H03K3/0322
摘要： An integrated circuit device includes a digitally controlled oscillator (DCO), two charge-sharing capacitors, two charge-sharing switches, two pre-charge switches, and two DACs. The DCO has a first inverter and a second inverter. A first charge-sharing capacitor has a first terminal coupled to an input terminal of the first inverter through a first charge-sharing switch. A first DAC has an output terminal coupled to the first terminal of the first charge-sharing capacitor through a first pre-charge switch. A second charge-sharing capacitor has a first terminal coupled to an input terminal or an output terminal of the second inverter through a second charge-sharing switch. A second DAC has an output terminal coupled to the first terminal of the second charge-sharing capacitor through a second pre-charge switch.
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