公开(公告)号：US09293184B2

公开(公告)日：2016-03-22

申请号：US14350434

申请日：2012-10-08

申请人： University of York

发明人： Kevin O'Grady ,  Gonzalo Vallejo Fernandez ,  Atsufumi Hirohata

IPC分类号： G11C19/00 ,  G11C19/02 ,  G11C7/00 ,  G11C11/00 ,  G11C5/02 ,  G11C19/38 ,  G11C11/16 ,  G11C11/14 ,  H04L12/26 ,  G11C19/08 ,  G11C14/00

CPC分类号： G11C11/1675 ,  G11C11/14 ,  G11C11/161 ,  G11C14/0081 ,  G11C19/02 ,  G11C19/0808 ,  G11C19/0833 ,  G11C19/085 ,  G11C19/0875 ,  H01L43/02 ,  H01L43/10 ,  H04L43/02 ,  H04L43/10

摘要： There is provided a method of pinning domain walls in a magnetic memory device (10) comprising using an antiferromagnetic material to create domain wall pinning sites. Junctions (22) where arrays of ferromagnetic nanowires (16) and antiferromagnetic nanowires (20) cross exhibit a permanent exchange bias interaction between the ferromagnetic material and the antiferromagnetic material which creates domain wall pinning sites. The exchange bias field is between 30 to 3600 Oe and the anisotropy direction of the ferromagnetic elements is between 15 to 75° to an anisotropy direction of the antiferromagnetic elements.

摘要翻译： 提供了一种在磁存储器装置（10）中钉扎畴壁的方法，包括使用反铁磁材料来产生畴壁钉扎位置。 铁磁性纳米线（16）和反铁磁性纳米线（20）交叉排列的结（22）在铁磁材料和反铁磁材料之间呈现永久的交换偏压相互作用，产生畴壁钉扎位置。 交换偏压场为30〜3600Oe，铁磁元件的各向异性方向与反铁磁性元件的各向异性方向成15〜75°。

公开(公告)号：US09165675B2

公开(公告)日：2015-10-20

申请号：US13970759

申请日：2013-08-20

申请人： International Business Machines Corporation

发明人： Anthony J. Annunziata

IPC分类号： G11C19/00 ,  G11C19/08 ,  H01L43/12 ,  G11C19/02 ,  H01L49/02 ,  H01L43/08 ,  G11C11/15

CPC分类号： G11C19/0808 ,  G11C11/15 ,  G11C19/02 ,  G11C19/0841 ,  H01L28/20 ,  H01L43/08 ,  H01L43/12 ,  Y10S977/762 ,  Y10S977/84 ,  Y10S977/943

摘要： A racetrack memory cell device include a dielectric, an electrode disposed in the dielectric, a metal strap disposed in the dielectric, a nanowire disposed in the dielectric between the electrode and the metal strap and a magnetic tunnel junction disposed in the dielectric on the metal strap, and axially with the nanowire.

公开(公告)号：US20150262702A1

公开(公告)日：2015-09-17

申请号：US14593334

申请日：2015-01-09

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Yasuaki OOTERA ,  Takuya SHIMADA ,  Shiho NAKAMURA

IPC分类号： G11C19/02

CPC分类号： G11C19/02 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C19/0808 ,  G11C19/0841

摘要： A magnetic memory according to an embodiment includes: a plurality of groups of magnetic nanowires extending in a direction, each group of magnetic nanowires including at least one magnetic nanowire, each magnetic nanowire having a first terminal and a second terminal; a plurality of recording and reproducing elements corresponding to the groups of magnetic nanowires, each recording and reproducing element writing data to and reading data from magnetic nanowires of a corresponding group of magnetic nanowires, and connecting to the first terminals of the magnetic nanowires of the corresponding group of magnetic nanowires; and an electrode to which the second terminals of the magnetic nanowires of the groups of magnetic nanowires are connected.

摘要翻译： 根据实施例的磁存储器包括：沿一个方向延伸的多组磁性纳米线组，每组磁性纳米线包括至少一个磁性纳米线，每个磁性纳米线具有第一端子和第二端子; 对应于磁纳米线组的多个记录和再现元件，每个记录和再现元件将数据写入并从相应的磁纳米线组的磁纳米线读取数据，并连接到相应的磁纳米线的第一端子 一组磁性纳米线; 以及连接有磁性纳米线组的磁性纳米线的第二端子的电极。

公开(公告)号：US09129679B2

公开(公告)日：2015-09-08

申请号：US13750085

申请日：2013-01-25

申请人： Kabushiki Kaisha Toshiba

发明人： Yoshiaki Fukuzumi ,  Hideaki Aochi

IPC分类号： G11C19/00 ,  G11C19/02 ,  G11C19/08 ,  H01L27/22 ,  H01L43/02 ,  B82Y10/00 ,  B82Y30/00 ,  G11C11/16 ,  G11C21/00

CPC分类号： G11C19/02 ,  B82Y10/00 ,  B82Y30/00 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C19/08 ,  G11C21/00 ,  H01L27/22 ,  H01L43/02

摘要： A shift register type magnetic memory according to an embodiment includes: a magnetic nanowire; a magnetic material chain provided in close vicinity to the magnetic nanowire, the magnetic material chain including a plurality of disk-shaped ferromagnetic films arranged along a direction in which the magnetic nanowire extends; a magnetization rotation drive unit configured to rotate and drive magnetization of the plurality of ferromagnetic films; a writing unit configured to write magnetic information into the magnetic nanowire; and a reading unit configured to read magnetic information from the magnetic nanowire.

摘要翻译： 根据实施例的移位寄存器型磁存储器包括：磁性纳米线; 磁性材料链，其设置在所述磁性纳米线附近，所述磁性材料链包括沿着所述磁性纳米线延伸的方向布置的多个盘状铁磁膜; 磁化旋转驱动单元，被配置为旋转并驱动所述多个铁磁性膜的磁化; 写入单元，被配置为将磁信息写入所述磁性纳米线; 以及读取单元，被配置为从磁性纳米线读取磁信息。

公开(公告)号：US20140268981A1

公开(公告)日：2014-09-18

申请号：US13835254

申请日：2013-03-15

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Anthony J. Annunziata ,  Marcin J. Gajek

IPC分类号： G11C19/02

CPC分类号： G11C19/0808 ,  G11C11/161 ,  G11C19/02 ,  G11C19/0816 ,  G11C19/0841

摘要： Embodiments are directed to injecting domain walls in a magnetic racetrack memory. In some embodiments, a racetrack comprising a nanowire is coupled with a gate in order to manipulate an anisotropy associated with the nanowire. The racetrack and gate is coupled with a pinning layer configured to establish a magnetization direction in the nanowire.

公开(公告)号：US11862216B2

公开(公告)日：2024-01-02

申请号：US17927535

申请日：2021-10-27

申请人： CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD. ,  BOE TECHNOLOGY GROUP CO., LTD.

发明人： Zhu Wang ,  Ling Shi ,  Yipeng Chen ,  Hui Lu ,  Zhenglong Yan ,  Changchang Liu ,  Ke Liu

IPC分类号： G11C19/02 ,  G09G3/3233 ,  G09G3/3266 ,  G11C19/28

CPC分类号： G11C19/28 ,  G09G3/3233 ,  G09G3/3266 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2310/0286 ,  G09G2310/08

摘要： A shift register, comprising an input circuit, a first control circuit, a second control circuit and an output circuit. The input circuit is configured to transmit a first voltage signal from a first voltage signal terminal to a first node under the control of an input signal from a signal input terminal. The first control circuit is configured to transmit a second voltage signal from a second voltage signal terminal to a second node under the control of a first clock signal from a first clock signal terminal and the voltage of the first node. The second control circuit is configured to transmit a second clock signal from a second clock signal terminal to a third node under the control of the voltage of the second node. The output circuit is configured to transmit the first voltage signal from the first voltage signal terminal to a scan signal output terminal under the control of the voltage of the third node.

公开(公告)号：US10403810B2

公开(公告)日：2019-09-03

申请号：US15978042

申请日：2018-05-11

申请人： The Curators of the University of Missouri

发明人： Deepak Kumar Singh ,  Brock Summers ,  Ashutosh Dahal

IPC分类号： G11C11/16 ,  G11C11/56 ,  G11C19/02 ,  H01F10/14 ,  H01F10/26 ,  H01F41/20 ,  H01F41/34 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

摘要： A magnetic artificial honeycomb lattice comprising a multiplicity of connecting elements separated by hexagonal cylindrical pores, wherein: (a) the hexagonal cylindrical pores: (i) have widths that are substantially uniform and an average width that is in a range of about 15 nm to about 20 nm; and (ii) are substantially equispaced and have an average center-to-center distance that is in a range of about 25 nm to about 35 nm; and (b) the connecting elements comprise a magnetic material layer, and the connecting elements have: (i) lengths that are substantially uniform and an average length that is in a range of about 10 nm to about 15 nm; (ii) widths that are substantially uniform and an average width that is in a range of about 4 nm to about 8 nm; and (iii) a thickness of the magnetic material layer that is substantially uniform and an average thickness that is in a range of about 2 nm to about 8 nm; and (c) the magnetic artificial honeycomb lattice has a surface area, disregarding the presence of the hexagonal cylindrical pores, that is in a range in a range of about 100 mm2 to about 900 mm2.

公开(公告)号：US10084126B1

公开(公告)日：2018-09-25

申请号：US15661026

申请日：2017-07-27

申请人： TOSHIBA MEMORY CORPORATION

发明人： Michael Arnaud Quinsat ,  Takuya Shimada ,  Tsuyoshi Kondo

IPC分类号： G11C19/00 ,  H01L43/02 ,  H01L43/10 ,  H01L43/08 ,  G11C11/16 ,  G11C19/02

摘要： According to one embodiment, a magnetic memory device includes first and second magnetic members, and a conductive member. The first magnetic member includes first, second, and third extending portions. The first extending portion extends along a first direction. The second extending portion extends along a second direction. The third extending portion includes a third connection portion connected with the first and second extending portions. The third extending portion extends along a third direction. The conductive member extends along a fourth direction. The first and second directions are inclined with respect to the fourth direction. The conductive member includes a portion overlapping at least parts of the first and second extending portions in a fifth direction. The fifth direction crosses the first, the second and the fourth directions. The conductive member includes a metal. A direction from the third extending portion toward the second magnetic member crosses the third direction.

公开(公告)号：US09466363B2

公开(公告)日：2016-10-11

申请号：US14369974

申请日：2012-12-04

申请人： TOHOKU UNIVERSITY

发明人： Tetsuo Endoh ,  Takashi Ohsawa ,  Hiroki Koike ,  Takahiro Hanyu ,  Hideo Ohno

IPC分类号： G11C14/00 ,  G11C13/00 ,  G11C11/16 ,  G11C15/04 ,  G11C19/02 ,  H03K3/356 ,  H03K3/59 ,  H03K19/18 ,  G11C29/50

CPC分类号： G11C13/0038 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0069 ,  G11C14/00 ,  G11C14/0081 ,  G11C15/046 ,  G11C19/02 ,  G11C29/50012 ,  H03K3/356139 ,  H03K3/59 ,  H03K19/18

摘要： An integrated circuit that does not involve increase in power consumption or decrease in switching probability during a write operation that occur when a latch circuit using STT-MTJ device, etc. of the prior art is operated at high speed is provided. The integrated circuit 1 includes: a memory element 1B where write occurs when a specified period τ has elapsed after a write signal is input; and a basic circuit element 1A, which is an elementary device constituting a circuit and has a data retaining function, and characterized in that an operation frequency f1 in a first operation mode in the process of memory access of the basic circuit element 1A satisfies the following relation: τ>λ1/f1(0

公开(公告)号：US09190167B2

公开(公告)日：2015-11-17

申请号：US13935763

申请日：2013-07-05

申请人： Kabushiki Kaisha Toshiba

发明人： Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Hirofumi Morise

IPC分类号： G11C19/00 ,  G11C19/02 ,  G11C19/08

CPC分类号： G11C19/02 ,  G11C19/08

摘要： A shift register according to an embodiment includes: a magnetic nanowire; a first control electrode group and a second control electrode group arranged with the magnetic nanowire being sandwiched therebetween, the first control electrode group including a plurality of first control electrodes arranged to be spaced apart from each other along a direction in which the magnetic nanowire extends, the second control electrode group including a plurality of second control electrodes arranged to be spaced apart from each other to correspond to the plurality of first control electrodes along the direction in which the magnetic nanowire extends, and the second control electrodes corresponding to the first control electrodes being shifted in the direction in which the magnetic nanowire extends; a first driving unit for driving the first control electrode group; and a second driving unit for driving the second control electrode group.

摘要翻译： 根据实施例的移位寄存器包括：磁性纳米线; 所述第一控制电极组和所述磁性纳米线夹在其间的第二控制电极组，所述第一控制电极组包括沿着所述磁性纳米线延伸的方向彼此间隔开的多个第一控制电极， 所述第二控制电极组包括多个第二控制电极，所述多个第二控制电极被布置为沿着所述多个第一控制电极沿着所述磁性纳米线延伸的方向彼此间隔开，并且所述第二控制电极对应于所述第一控制电极 沿着磁性纳米线延伸的方向移动; 用于驱动第一控制电极组的第一驱动单元; 以及用于驱动第二控制电极组的第二驱动单元。