公开(公告)号：US10917094B2

公开(公告)日：2021-02-09

申请号：US16445945

申请日：2019-06-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Qing Meng

IPC: H03K19/00 ,  G11C19/28 ,  G11C19/38

Abstract: Systems, apparatuses, and methods for implementing stripe-based self-gating and change detect signal propagation for retiming pipelines are disclosed. A circuit includes one or more stripes, with each stripe including a plurality of stages of registers, with each stage only receiving input signals from the preceding stage. For a given stripe, the first stage of registers are self-gated to reduce power consumption by only clocking a group of registers when any of their input signals change. The self-gating signals of the first stage of registers are combined together to create a change detect signal which is passed through a register and provided to a second stage of registers as a clock-enable signal. Accordingly, the second stage registers are only clocked when the change detect signal indicates a change will be forwarded from the first stage. This reduces power consumption for the second stage without causing the area increase associated with self-gating circuitry.

公开(公告)号：US20200381069A1

公开(公告)日：2020-12-03

申请号：US16445945

申请日：2019-06-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Qing Meng

IPC: G11C19/28 ,  G11C19/38

Abstract: Systems, apparatuses, and methods for implementing stripe-based self-gating and change detect signal propagation for retiming pipelines are disclosed. A circuit includes one or more stripes, with each stripe including a plurality of stages of registers, with each stage only receiving input signals from the preceding stage. For a given stripe, the first stage of registers are self-gated to reduce power consumption by only clocking a group of registers when any of their input signals change. The self-gating signals of the first stage of registers are combined together to create a change detect signal which is passed through a register and provided to a second stage of registers as a clock-enable signal. Accordingly, the second stage registers are only clocked when the change detect signal indicates a change will be forwarded from the first stage. This reduces power consumption for the second stage without causing the area increase associated with self-gating circuitry.

公开(公告)号：US10607558B2

公开(公告)日：2020-03-31

申请号：US15787900

申请日：2017-10-19

Applicant: AU Optronics Corporation

Inventor： Peng-Bo Xi ,  Sung-Yu Su

IPC: G09G3/36 ,  G11C19/38 ,  G11C19/28 ,  G09G3/3266

Abstract: A gate driving circuit includes a plurality of shift register circuits, where the shift register circuits are configured to drive a plurality of pixel rows. The gate driving circuit may be operated in a first mode and a second mode. When the gate driving circuit is operated in the first mode, the gate driving circuit is configured to drive, in a single frame, all pixel rows to be displayed. When the gate driving circuit is operated in the second mode, the gate driving circuit is configured to drive, in the single frame, some of the pixel rows to be displayed, and driven pixel rows of two adjacent frames are different.

公开(公告)号：US10539539B2

公开(公告)日：2020-01-21

申请号：US15589921

申请日：2017-05-08

Applicant: InvenSense, Inc.

Inventor： Bruno W. Garlepp ,  Michael H. Perrott ,  James Christian Salvia

IPC: G01N29/34 ,  G11C19/28 ,  G11C19/38 ,  B06B1/06 ,  G10K11/34 ,  H01L41/047 ,  H01L41/113 ,  H03K17/96

Abstract: In a method of using an ultrasonic sensor comprising a two-dimensional array of ultrasonic transducers, a plurality of ultrasonic signals are transmitted according to a beamforming pattern at a position of the two-dimensional array. The beamforming pattern focuses the plurality of ultrasonic signals to location above the two-dimensional array, wherein the beamforming pattern identifies ultrasonic transducers of the two-dimensional array that are activated during transmission of the ultrasonic signals, and wherein at least some ultrasonic transducers of the beamforming pattern are phase delayed with respect to other ultrasonic transducers of the beamforming pattern. At least one reflected ultrasonic signal is received at the position according to a receive pattern, wherein the receive pattern identifies at least one ultrasonic transducers of the two-dimensional array that is activated during the receiving. The transmitting and the receiving are repeated at a plurality of positions of the two-dimensional array.

公开(公告)号：US10477164B2

公开(公告)日：2019-11-12

申请号：US15595403

申请日：2017-05-15

Applicant: Google LLC

Inventor： Jason Rupert Redgrave

IPC: H04N9/04 ,  G06T1/20 ,  G11C19/38 ,  H04N5/907 ,  G06F15/173 ,  G06F15/80 ,  G11C7/10 ,  H01P5/12 ,  H03K19/177 ,  G11C19/00 ,  G11C19/28

Abstract: A shift register is described. The shift register includes a plurality of cells and register space. The shift register includes circuitry having inputs to receive shifted data and outputs to transmit shifted data, wherein: i) circuitry of cells physically located between first and second logically ordered cells are configured to not perform any logical shift; ii) circuitry of cells coupled to receive shifted data transmitted by an immediately preceding logically ordered cell comprises circuitry for writing into local register space data received at an input assigned an amount of shift specified in a shift command being executed by the shift register, and, iii) circuitry of cells coupled to transmit shifted data to an immediately following logically ordered cell comprises circuitry to transmit data from an output assigned an incremented shift amount from a shift amount of an input that the data was received on.

公开(公告)号：US10313641B2

公开(公告)日：2019-06-04

申请号：US15352260

申请日：2016-11-15

Applicant: Google LLC

Inventor： Jason Rupert Redgrave

IPC: G06T1/20 ,  G11C7/10 ,  H01P5/12 ,  H04N9/04 ,  G06F15/80 ,  G11C19/00 ,  G11C19/28 ,  G11C19/38 ,  H04N5/907 ,  G06F15/173 ,  H03K19/177

Abstract: A shift register is described. The shift register includes a plurality of cells and register space. The shift register includes circuitry having inputs to receive shifted data and outputs to transmit shifted data, wherein: i) circuitry of cells physically located between first and second logically ordered cells are configured to not perform any logical shift; ii) circuitry of cells coupled to receive shifted data transmitted by an immediately preceding logically ordered cell comprises circuitry for writing into local register space data received at an input assigned an amount of shift specified in a shift command being executed by the shift register, and, iii) circuitry of cells coupled to transmit shifted data to an immediately following logically ordered cell comprises circuitry to transmit data from an output assigned an incremented shift amount from a shift amount of an input that the data was received on.

公开(公告)号：US20180329479A1

公开(公告)日：2018-11-15

申请号：US15595600

申请日：2017-05-15

Applicant: Google Inc.

Inventor： Albert MEIXNER

IPC: G06F3/00 ,  G11C19/38 ,  G06T7/73 ,  H04N19/44

CPC classification number: G06F3/007 ,  G06T1/20 ,  G06T7/73 ,  G11C19/38 ,  H04N19/44

Abstract: An image processor is described. The image processor includes a two dimensional shift register array that couples certain ones of its array locations to support execution of a shift instruction. The shift instruction is to include mask information. The mask information is to specify which of the array locations are to be written to with information being shifted. The two dimensional shift register array includes masking logic circuitry to write the information being shifted into specified ones of the array locations in accordance with the mask information.

公开(公告)号：US4975640A

公开(公告)日：1990-12-04

申请号：US482458

申请日：1990-02-20

Applicant: Robert J. Lipp

Inventor： Robert J. Lipp

IPC: G06F11/27 ,  G11C19/00 ,  G11C19/38

CPC classification number: G11C19/38 ,  G06F11/27 ,  G11C19/00

Abstract: A method for operating a multiple input linear feedback shift register (LFSR) as a conventional shift register so that input multiplexers can be eliminated on each parallel input when associated with a CrossCheck matrix. A linear feedback shift register coupled through sense lines of a CrossCheck test matrix is operated as a serial shift register by inputting serial data at the serial data input while maintaining parallel input lines at a zero logic level. Further, zero logic level serial data (null data) is input serially through the shift register prior to the enabling of the parallel input. The method significantly reduces the number of logic structures required to shift the data out serially.

公开(公告)号：US4872137A

公开(公告)日：1989-10-03

申请号：US800509

申请日：1985-11-21

Applicant: Earle W. Jennings, III

Inventor： Earle W. Jennings, III

IPC: G11C19/00 ,  G11C19/38 ,  G11C29/00 ,  H03K19/173 ,  H03K19/177

CPC classification number: G11C19/38 ,  G11C19/00 ,  G11C29/006 ,  H03K19/1736 ,  H03K19/17712

Abstract: In the present invention, a reprogrammable control circuit is disclosed. The reprogrammable control circuit comprises a single-bit register for serially receiving an input bit signal and providing a control signal. The control signal represents the state of the bit stored in the register. A transmission gate means receives the control signal from the single-bit shift register and an input signal and provides an output signal therefrom. The control signal of the bit shift register is used to control the transmission of the input signal to the output signal. A plurality of reprogrammable control circuit which comprises a plurality of bit shift registers, each having a transmission gate means associated therewith is also disclosed. The reprogrammable control circuit can be used in an improved PLA, improved RAM, improved RCIM, improved ALU, improved counter, improved CAM, PCN to improve the reliability of routing signals and power, and to preserve the states of flip-flops. The improved digital control circuits can then be effectively integrated on a wafer scale.

Abstract translation: 在本发明中，公开了一种可再编程控制电路。 可再编程控制电路包括用于串行接收输入位信号并提供控制信号的单位寄存器。 控制信号表示存储在寄存器中的位的状态。 传输门装置接收来自单位移位寄存器的控制信号和输入信号，并从其提供输出信号。 位移寄存器的控制信号用于控制输入信号到输出信号的传输。 还公开了包括多个位移寄存器的多个可再编程控制电路，每个具有与之相关联的传输门装置。 可编程控制电路可用于改进的PLA，改进的RAM，改进的RCIM，改进的ALU，改进的计数器，改进的CAM，PCN，以提高路由信号和功率的可靠性，并保持触发器的状态。 因此，改进的数字控制电路可以有效地集成在晶片规模上。

公开(公告)号：US3811110A

公开(公告)日：1974-05-14

申请号：US27442272

申请日：1972-07-24

Applicant: INOSE F ,  KITA Y

Inventor： KITA Y ,  INOSE F

IPC: G06K9/32 ,  G11C19/08 ,  G11C19/38 ,  G06K9/04

CPC classification number: G06K9/3283 ,  G11C19/0866 ,  G11C19/0875 ,  G11C19/38

Abstract: An arrangement for normalizing a two-dimensional pattern, wherein a pattern input unit and a pattern detecting unit are respectively provided along the X-axis and Y-axis of a memory array which provides a shift function in the X- and Y-directions, and wherein said pattern detecting unit is arranged at certain angles with respect to the X-axis and Y-axis of said memory array, whereby the two-dimensional pattern stored in said memory array is successively shifted in the X-direction and Y-direction so as to impart rotation to said pattern.

Abstract translation: 一种用于归一化二维图案的装置，其中分别沿着在X和Y方向上提供移位功能的存储器阵列的X轴和Y轴设置图案输入单元和图案检测单元， 并且其中所述图案检测单元相对于所述存储器阵列的X轴和Y轴以一定角度布置，由此存储在所述存储器阵列中的二维图案在X方向和Y方向上连续移位 以便赋予所述图案旋转。