公开(公告)号：US20180083634A1

公开(公告)日：2018-03-22

申请号：US15823216

申请日：2017-11-27

Applicant: Microsemi SoC Corp.

Inventor： John L. McCollum ,  Esmat Z. Hamdy

IPC: H03K19/177 ,  H01L27/24 ,  G11C13/00 ,  H01L45/00

CPC classification number: H03K19/1776 ,  G11C13/0026 ,  G11C13/003 ,  G11C13/0069 ,  G11C2213/79 ,  H01L24/26 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/12 ,  H03K19/0941

Abstract: A low-leakage resistive random access memory cell includes a complementary pair of bit lines and a switch node. A first ReRAM device is connected to a first one of the bit lines. A p-channel transistor has a source connected to the ReRAM device, a drain connected to the switch node, and a gate connected to a bias potential. A second ReRAM device is connected to a second one of the bit lines. An n-channel transistor has a source connected to the ReRAM device a drain connected to the switch node, and a gate connected to a bias potential.

公开(公告)号：US08207775B2

公开(公告)日：2012-06-26

申请号：US12871343

申请日：2010-08-30

Applicant: Chan-Hong Chern ,  Fu-Lung Hsueh ,  Yuwen Swei ,  Chih-Chang Lin

Inventor： Chan-Hong Chern ,  Fu-Lung Hsueh ,  Yuwen Swei ,  Chih-Chang Lin

IPC: H03L5/00

CPC classification number: H03K19/0941 ,  H03K3/356182 ,  H03K19/018514

Abstract: A representative level-shifter comprises a dynamically biased current source circuit that receives a first voltage, a first and a second unidirectional current-conducting devices, a first and a second pull-down devices, and a pull-up device. The first and second unidirectional current-conducting devices are coupled to the dynamically biased current source circuit. A voltage output of the level-shifter is located at a first node that is located between the current-constant circuit and the second unidirectional current-conducting device. The first and second pull-down devices are coupled to the first and second unidirectional current-conducting devices, respectively. The pull-up device receives a second voltage and is coupled to the dynamically biased current source circuit and the first unidirectional current-conducting device. The pull-up device is configured to dynamically bias the dynamically biased current source circuit such that a voltage drop of the second unidirectional current-conducting device is output at the voltage output responsive to the pull-up device outputting the second voltage to the dynamically biased current source circuit, the first pull-down device being non-conducting and the second pull-down device being conducting.

Abstract translation: 代表性的电平转换器包括接收第一电压，第一和第二单向导流器件，第一和第二下拉器件以及上拉器件的动态偏置电流源电路。 第一和第二单向导流器件耦合到动态偏置电流源电路。 电平移位器的电压输出位于位于电流恒定电路和第二单向导流器件之间的第一节点处。 第一和第二下拉装置分别耦合到第一和第二单向导流装置。 上拉装置接收第二电压并耦合到动态偏置电流源电路和第一单向导流装置。 上拉装置被配置为动态地偏置动态偏置的电流源电路，使得第二单向导流装置的电压降在电压输出处被输出，响应于上拉装置将第二电压输出到动态偏置 电流源电路，第一下拉装置不导通，第二下拉装置导通。

公开(公告)号：US20120050930A1

公开(公告)日：2012-03-01

申请号：US12871343

申请日：2010-08-30

Applicant: Chan-Hong CHERN ,  Fu-Lung HSUEH ,  Yuwen SWEI ,  Chih-Chang LIN

Inventor： Chan-Hong CHERN ,  Fu-Lung HSUEH ,  Yuwen SWEI ,  Chih-Chang LIN

IPC: H02H9/04 ,  H03L5/00

CPC classification number: H03K19/0941 ,  H03K3/356182 ,  H03K19/018514

Abstract: A representative level-shifter comprises a dynamically biased current source circuit that receives a first voltage, a first and a second unidirectional current-conducting devices, a first and a second pull-down devices, and a pull-up device. The first and second unidirectional current-conducting devices are coupled to the dynamically biased current source circuit. A voltage output of the level-shifter is located at a first node that is located between the current-constant circuit and the second unidirectional current-conducting device. The first and second pull-down devices are coupled to the first and second unidirectional current-conducting devices, respectively. The pull-up device receives a second voltage and is coupled to the dynamically biased current source circuit and the first unidirectional current-conducting device. The pull-up device is configured to dynamically bias the dynamically biased current source circuit such that a voltage drop of the second unidirectional current-conducting device is output at the voltage output responsive to the pull-up device outputting the second voltage to the dynamically biased current source circuit, the first pull-down device being non-conducting and the second pull-down device being conducting.

Abstract translation: 代表性的电平转换器包括接收第一电压，第一和第二单向导流器件，第一和第二下拉器件以及上拉器件的动态偏置电流源电路。 第一和第二单向导流器件耦合到动态偏置电流源电路。 电平移位器的电压输出位于位于电流恒定电路和第二单向导流器件之间的第一节点处。 第一和第二下拉装置分别耦合到第一和第二单向导流装置。 上拉装置接收第二电压并耦合到动态偏置电流源电路和第一单向导流装置。 上拉装置被配置为动态地偏置动态偏置的电流源电路，使得第二单向导流装置的电压降在电压输出处被输出，响应于上拉装置将第二电压输出到动态偏置 电流源电路，第一下拉装置不导通，第二下拉装置导通。

公开(公告)号：US4954730A

公开(公告)日：1990-09-04

申请号：US342224

申请日：1989-04-21

Applicant: Kanji Yoh

Inventor： Kanji Yoh

IPC: H03K19/094 ,  H03K19/0952

CPC classification number: H03K19/0952 ,  H03K19/0941

Abstract: A merged enhancement/depletion-mode FET circuit and a complementary FET logic circuit have enhanced operation speed and reduced power dissipation. Serially connected depletion mode and enhancement mode transistors function as an output stage for the complementary FET logic stage, with the gate of an n-channel enhancement-mode transistor being connected to the output of the complementary FET logic stage and the output of an n-channel depletion-mode transistor being connected to the common terminal or output terminal of the output stage. In an alternative embodiment, a p-channel enhancement-mode transistor is connected in parallel with the n-channel depletion-mode transistor with the gate of the p-channel enhancement-mode transistor being connected to the output of the complementary FET logic stage. The circuitry is particularly useful in compound semiconductor circuits using MESFETS and heterojunction-FETs.

Abstract translation: 合并的增强/耗尽型FET电路和互补FET逻辑电路具有增强的操作速度和降低的功率耗散。 串联耗尽模式和增强型晶体管用作互补FET逻辑级的输出级，其中n沟道增强型晶体管的栅极连接到互补FET逻辑级的输出， 沟道耗尽型晶体管连接到输出级的公共端或输出端。 在替代实施例中，p沟道增强型晶体管与n沟道耗尽型晶体管并联连接，p沟道增强型晶体管的栅极连接到互补FET逻辑级的输出。 该电路在使用MESFETS和异质结FET的化合物半导体电路中特别有用。

公开(公告)号：US20240355833A1

公开(公告)日：2024-10-24

申请号：US18599439

申请日：2024-03-08

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takahiko ISHIZU ,  Seiichi YONEDA

IPC: H01L27/12 ,  H01L29/24 ,  H03K19/003 ,  H03K19/017 ,  H03K19/094 ,  H03K19/20

CPC classification number: H01L27/124 ,  H01L27/1259 ,  H01L29/24 ,  H03K19/00315 ,  H03K19/017 ,  H03K19/0941 ,  H03K19/20

Abstract: A semiconductor device capable of stable operation with low power consumption is provided. A logic circuit having a circuit configuration using a transistor including an oxide semiconductor in a channel formation region is included. The logic circuit is a two-input/two-output two-wire logic circuit. Transistors included in the logic circuit each include a gate and a back gate. An input terminal is electrically connected to one of a gate and a back gate of a transistor electrically connected to a wiring for supplying a high power supply potential. An output terminal is connected to the other of the gate and the back gate of the transistor electrically connected to the wiring for supplying a high power supply potential. An output terminal is electrically connected to one of a source and a drain of a transistor electrically connected to a wiring for supplying a low power supply potential. A gate or a back gate of the transistor electrically connected to the wiring for supplying a low power supply potential is electrically connected to an input terminal.

公开(公告)号：US09479174B2

公开(公告)日：2016-10-25

申请号：US14364923

申请日：2012-12-11

Applicant: Soitec

Inventor： Richard Ferrant

IPC: H03K19/094 ,  H01L27/088 ,  H01L27/12

CPC classification number: H03K19/09429 ,  H01L27/0886 ,  H01L27/1203 ,  H03K19/094 ,  H03K19/0941

Abstract: A tristate gate includes an output port and at least two transistors. Each of the transistors has at least a first and a second gate configured such that a high-impedance value (Z) on the output port is set by controlling the threshold voltage of at least one of the transistors.

Abstract translation: 三态门包括输出端口和至少两个晶体管。 每个晶体管具有至少第一和第二栅极，其配置为使得通过控制至少一个晶体管的阈值电压来设置输出端口上的高阻抗值（Z）。

公开(公告)号：US09276573B2

公开(公告)日：2016-03-01

申请号：US14444422

申请日：2014-07-28

Applicant: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)

Inventor： Pierre-Emmanuel Gaillardon ,  Xifan Tang ,  Giovanni De Micheli

IPC: H03K19/177 ,  H03K19/00 ,  H03K19/094

CPC classification number: H03K19/0013 ,  H03K19/0941 ,  H03K19/17728 ,  H03K19/1774 ,  H03K19/1776

Abstract: A Field Programmable Gate Array (FPGA) of the island-type comprising a plurality of cluster-based Configurable Logic Blocks (CLBs), whereby each of the cluster-based CLBs is surrounded by a global routing structure formed by a plurality of multiplexers and pass/transmission-gates organized in Switch Boxes (SBs) and Connection Blocks (CBs), the switch boxes and the connection blocks comprising at least a first plurality of resistive memories inserted in a data path of a first routing architecture of the switch boxes and the connection blocks. Each CLB contains Basic Logic Elements (BLEs), as well as local routing resources.

Abstract translation: 岛型的现场可编程门阵列（FPGA）包括多个基于簇的可配置逻辑块（CLB），由此基于簇的CLB中的每一个由由多个多路复用器形成的全局路由结构包围并通过 组合在开关盒（SB）和连接块（CB）中的传输门），开关盒和连接块包括至少插入在开关盒的第一路由架构的数据路径中的第一多个电阻存储器，以及 连接块。 每个CLB都包含基本逻辑元素（BLE）以及本地路由资源。

公开(公告)号：US08086657B2

公开(公告)日：2011-12-27

申请号：US12099973

申请日：2008-04-09

Applicant: Wilhelm Haller ,  Rolf Sautter ,  Christoph Wandel ,  Ulrich Weiss

Inventor： Wilhelm Haller ,  Rolf Sautter ,  Christoph Wandel ,  Ulrich Weiss

IPC: G06F7/50

CPC classification number: H03K19/0941 ,  H03K19/0008

Abstract: A digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage implementing a predetermined logic function and processing input variables from a preceding stage and outputting result values to a succeeding stage static and dynamic logic in the carry network of a 4-bit adder, and with output from the first stage fed directly as an input (60, 62) to the third stage of the carry network. Preferably, stages having normally relatively high switching activities are implemented in static logic. Preferably, the first stage of its carry network is implemented in a static logic, and the rest of the stages in dynamic logic.

Abstract translation: 一种数字加法器电路，包括在所述加法器电路的进位逻辑中的多个逻辑级，用于产生和传播预定的操作数位组，每个级实现预定的逻辑功能，并处理来自前一级的输入变量，并将结果值输出到 4位加法器的进位网络中的后级静态和动态逻辑，并且来自第一级的输出直接作为输入（60,62）馈送到进位网络的第三级。 优选地，具有通常相对较高切换活动的阶段在静态逻辑中实现。 优选地，其进位网络的第一级是以静态逻辑实现的，其余的级在动态逻辑中。

公开(公告)号：US07498845B1

公开(公告)日：2009-03-03

申请号：US11880648

申请日：2007-07-23

Applicant: James T. Doyle

Inventor： James T. Doyle

IPC: H03K19/096

CPC classification number: H03K19/00346 ,  H03K19/0941

Abstract: Leakage currents at IC inputs can be avoided while the IC is disabled by providing a switch that is responsive to deactivation of an enable input to isolate functional circuitry of the IC from one of the power supply nodes of the IC. This eliminates power supply current while the IC is disabled. Further unwanted current flow can be avoided while the IC is disabled by providing a switch that is responsive to the enable input for selectively connecting and disconnecting the base of a reference voltage transistor to and from the transistor's grounded collector, which collector is defined by the substrate of the IC. Disconnection of the base from the grounded substrate/collector eliminates base current and thus prevents emitter-to-collector current flow through the transistor when the IC is disabled.

Abstract translation: 可以通过提供响应于使能输入的去激活而将IC与IC的电源节点之一隔离的开关来禁用IC来禁止IC输入端的泄漏电流。 这可以在IC禁用时消除电源电流。 通过提供响应于使能输入的开关来禁用IC，可以避免IC的不需要的电流流动，该开关用于选择性地将参考电压晶体管的基极连接到晶体管的接地集电极和从晶体管的接地集电极断开，该集电极由衬底 的IC。 基极与接地的基板/集电极的断开消除了基极电流，因此当IC被禁用时，防止发射极到集电极电流流过晶体管。

公开(公告)号：US12095458B2

公开(公告)日：2024-09-17

申请号：US17825378

申请日：2022-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Umamaheswara Reddy Katta ,  Tamal Das

IPC: H03K19/0185 ,  H03K19/017 ,  H03K19/094 ,  H03K19/20

CPC classification number: H03K19/01855 ,  H03K19/01742 ,  H03K19/0941 ,  H03K19/20

Abstract: A method, implemented in a serializer for quarter rate serialization, is disclosed. The method includes receiving a plurality of in-phase and quarter-phase clock signals defining a quarter phase clock. The method includes receiving a quarter rate data input and sequentially outputting data in accordance with the quarter phase clock. The method includes receiving at least one data input from amongst the quarter rate input and outputting a first logical output in accordance with the in-phase clock signal and the quarter-phase clock signal. The method includes receiving said at least one data input and outputting a second logical output in accordance a complementary in-phase clock signal and a complementary quarter-phase clock signal. The method includes outputting, an output associated with the branch.