公开(公告)号：US20220236785A1

公开(公告)日：2022-07-28

申请号：US17614409

申请日：2020-05-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Takahiko ISHIZU ,  Tatsuya ONUKI ,  Hitoshi KUNITAKE

IPC: G06F1/3287 ,  H01L27/108 ,  H01L27/11

Abstract: A semiconductor device with low power consumption is provided. The semiconductor device includes a power management unit, a CPU core, and a memory device, the power management unit includes a power switch and a power controller, and the memory device includes a working memory and a long-term memory storage portion. The power switch has a function of controlling supply of a power supply voltage to the CPU core and the memory device, and the power controller has a function of controlling operation of the power switch. The CPU core has a function of transmitting a timing of stopping the supply of the power supply voltage to the power controller, and the memory device has a function of saving data retained in the working memory to the long-term memory storage portion before the supply of the power supply voltage is stopped by the power switch. Transistors included in each of the power management unit and the CPU core are preferably Si transistors.

公开(公告)号：US20220094177A1

公开(公告)日：2022-03-24

申请号：US17422314

申请日：2020-01-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuki OKAMOTO ,  Takahiko ISHIZU ,  Kei TAKAHASHI ,  Takayuki IKEDA

IPC: H02J7/00

Abstract: A battery control circuit having a novel structure, a battery protection circuit having a novel structure, and a power storage device including the battery circuit are provided. A semiconductor device includes n cell balancing circuits that respectively correspond to one secondary battery and each include a transistor, a comparator circuit, and a capacitor. In each of the n cell balancing circuits, an inverting input terminal of the comparator circuit and one electrode of the capacitor are electrically connected to one of a source and a drain of the transistor. The semiconductor device has functions of supplying a ground potential to the other electrode of the capacitor; turning on the transistor; supplying a first potential to the one electrode of the capacitor; turning off the transistor; electrically connecting the other electrode of the capacitor and a negative electrode of the secondary battery corresponding to each cell balancing circuit; supplying a sum of the first potential and a potential of the negative electrode of the secondary battery corresponding to each cell balancing circuit, to the one electrode of the capacitor; and controlling charging of the secondary battery corresponding to each cell balancing circuit.

公开(公告)号：US20220077705A1

公开(公告)日：2022-03-10

申请号：US17417482

申请日：2019-12-18

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kei TAKAHASHI ,  Takayuki IKEDA ,  Munehiro KOZUMA ,  Takanori MATSUZAKI ,  Takahiko ISHIZU ,  Takeshi AOKI

IPC: H02J7/00

Abstract: A secondary battery deteriorates due to repeated charging and discharging, which leads to a decrease in a battery voltage and a battery capacity. The lifetime of a secondary battery is prolonged by preventing charging at an excessive charging value that would be caused by deterioration of the secondary battery. By performing charge control in consideration of the degree of deterioration of a secondary battery, a longer lifetime of a secondary battery can be achieved. In charging a secondary battery, a charge control circuit controls a current value to a preset value, and a charging current control circuit (specifically a circuit including an error amplifier) included in a protection circuit determines a current value supplied to the secondary battery. That is, the current value supplied to the secondary battery is controlled by both the charge control circuit and the charging current control circuit that is a part of the protection circuit.

公开(公告)号：US20210242690A1

公开(公告)日：2021-08-05

申请号：US17269330

申请日：2019-08-21

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yuki OKAMOTO ,  Takahiko ISHIZU

IPC: H02J7/00 ,  H01L29/786 ,  H01L27/12 ,  H01M10/42 ,  H01M10/44

Abstract: To provide a battery control circuit with a novel structure, a battery protection circuit with a novel structure, and a power storage device including the battery circuit. The semiconductor device includes n cell-balance circuits (n is an integer greater than or equal to 1). One secondary battery is electrically connected to one cell-balance circuit. The cell-balance circuit includes a comparison circuit, and a memory element is electrically connected to an inverting input terminal of the comparison circuit. The memory element includes a first transistor and a capacitor. A potential is retained. The retained potential changes in accordance with a change in a potential of a negative electrode of the secondary battery. The comparison circuit has a function of comparing the retained potential with a potential of a positive electrode of the secondary battery. Output from the comparison circuit controls a gate voltage of a second transistor electrically connected to the secondary battery in parallel. The first transistor includes a metal oxide including indium in a channel formation region.

公开(公告)号：US20200013453A1

公开(公告)日：2020-01-09

申请号：US16572784

申请日：2019-09-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko ISHIZU ,  Hikaru TAMURA

IPC: G11C11/419 ,  G11C11/401 ,  G11C11/4076 ,  G11C11/4096 ,  H01L23/544 ,  H01L27/105 ,  H01L29/786

Abstract: A memory in which a write cycle time is longer than time for one clock cycle can be mounted on a processor. The processor includes a processor core, a bus, and a memory section. The memory section includes a first memory. A cell array of the first memory is composed of gain cells. The processor core is configured to generate a write enable signal. The first memory is configured to generate a wait signal on the basis of the write enable signal. The processor core is configured to delay access to the memory section by time for n clock cycles, on the basis of the wait signal. (n+1) clock cycles can be assigned to a write cycle of the first memory.

公开(公告)号：US20170221553A1

公开(公告)日：2017-08-03

申请号：US15415456

申请日：2017-01-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko ISHIZU ,  Hikaru TAMURA

IPC: G11C11/419 ,  H01L29/786 ,  H01L23/544 ,  H01L27/105

CPC classification number: G11C11/419 ,  G11C11/401 ,  G11C11/405 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/229 ,  H01L23/544 ,  H01L27/1052 ,  H01L29/7869

Abstract: A memory in which a write cycle time is longer than time for one clock cycle can be mounted on a processor. The processor includes a processor core, a bus, and a memory section. The memory section includes a first memory. A cell array of the first memory is composed of gain cells. The processor core is configured to generate a write enable signal. The first memory is configured to generate a wait signal on the basis of the write enable signal. The processor core is configured to delay access to the memory section by time for n clock cycles, on the basis of the wait signal. (n+1) clock cycles can be assigned to a write cycle of the first memory.

公开(公告)号：US20160351243A1

公开(公告)日：2016-12-01

申请号：US15160076

申请日：2016-05-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko ISHIZU ,  Shuhei NAGATSUKA ,  Tatsuya ONUKI ,  Yutaka SHIONOIRI ,  Naoaki TSUTSUI ,  Shunpei YAMAZAKI

IPC: G11C11/40 ,  H01L27/12 ,  G11C5/06 ,  G11C7/12 ,  G11C8/08 ,  H01L23/528 ,  H01L27/105 ,  G11C11/24

CPC classification number: H01L27/1207 ,  G11C5/063 ,  G11C11/401 ,  G11C11/4097 ,  G11C2029/0403 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/1255

Abstract: A memory device in which the number of films is reduced. The memory device includes a circuit and a wiring. The circuit includes a first memory cell and a second memory cell. The first memory cell includes a first transistor, a second transistor, and a first capacitor. The second memory cell includes a third transistor, a fourth transistor, and a second capacitor. The second memory cell is stacked over the first memory cell. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and the first capacitor. One of a source and a drain of the third transistor is electrically connected to a gate of the fourth transistor and the second capacitor. A gate of the first transistor and a gate of the third transistor are electrically connected to the wiring.

Abstract translation: 一种其中薄膜数量减少的存储器件。 存储器件包括电路和布线。 电路包括第一存储单元和第二存储单元。 第一存储单元包括第一晶体管，第二晶体管和第一电容器。 第二存储单元包括第三晶体管，第四晶体管和第二电容器。 第二存储单元堆叠在第一存储单元上。 第一晶体管的源极和漏极之一电连接到第二晶体管的栅极和第一电容器。 第三晶体管的源极和漏极之一电连接到第四晶体管和第二电容器的栅极。 第一晶体管的栅极和第三晶体管的栅极电连接到布线。

公开(公告)号：US20150348610A1

公开(公告)日：2015-12-03

申请号：US14723618

申请日：2015-05-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko ISHIZU

IPC: G11C11/406 ,  G11C11/4076

CPC classification number: G11C11/40615 ,  G11C11/404 ,  G11C11/405 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4091 ,  G11C2211/4068 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10805 ,  H01L27/1203 ,  H01L29/7841

Abstract: A memory device capable of optimizing a refresh cycle is provided. The memory device includes a monitor circuit capable of generating a signal serving as a trigger for a refresh operation. The monitor circuit includes a transistor and a capacitor. The monitor circuit has a function of sensing that a potential retained in the capacitor is lower than a reference potential, a function of generating a first signal and a second signal on the basis of the sensing result, and a function of turning on the transistor in response to the second signal and resetting the potential retained in the capacitor to an initialization state. It is possible to start refresh of a memory cell in response to the first signal.

Abstract translation: 提供了能够优化刷新周期的存储器件。 该存储装置包括能够产生用作刷新操作的触发信号的监视电路。 监视电路包括晶体管和电容器。 监视电路具有检测电容器中保持的电位低于参考电位的功能，基于感测结果产生第一信号和第二信号的功能以及将晶体管导通的功能 响应于第二信号并将保持在电容器中的电位重置为初始化状态。 可以响应于第一信号开始刷新存储器单元。

公开(公告)号：US20240304231A1

公开(公告)日：2024-09-12

申请号：US18657376

申请日：2024-05-07

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Kiyoshi KATO ,  Takahiko ISHIZU ,  Tatsuya ONUKI

IPC: G11C11/408 ,  H01L27/12 ,  H01L29/24 ,  H01L29/786 ,  H10B99/00

CPC classification number: G11C11/4085 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/24 ,  H01L29/78648 ,  H01L29/7869 ,  H10B99/00

Abstract: A memory device having long data retention time and high reliability is provided. The memory device includes a driver circuit and a plurality of memory cells, the memory cell includes a transistor and a capacitor, and the transistor includes a metal oxide in a channel formation region. The transistor includes a first gate and a second gate, and in a period during which the memory cell retains data, negative potentials are applied to the first gate and the second gate of the transistor.

公开(公告)号：US20230005528A1

公开(公告)日：2023-01-05

申请号：US17940065

申请日：2022-09-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko ISHIZU ,  Toshihiko SAITO ,  Hideki UOCHI ,  Shunpei YAMAZAKI

IPC: G11C11/419 ,  G11C11/409 ,  H01L29/04 ,  H01L29/786

Abstract: A novel memory device is provided. The memory device includes a plurality of memory cells, and one memory cell includes a first transistor and a second transistor. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor through a node SN. Data written through the first transistor is retained at the node SN. When an OS transistor is used as the first transistor, formation of a storage capacitor is not needed. A region with a low dielectric constant is provided outside the memory cell, whereby noise from the outside is reduced and stable operation is achieved.