公开(公告)号：US20180152188A1

公开(公告)日：2018-05-31

申请号：US15590443

申请日：2017-05-09

Applicant: Powerventure Semiconductor Limited

Inventor： Der Ju Hung ,  Yuan Wen Hsiao ,  Chi-Chia Huang

IPC: H03K19/0185 ,  H02M3/156 ,  G01S7/00 ,  H02J9/06 ,  H03K19/0948 ,  H03K19/094

CPC classification number: H02M3/156 ,  G01S7/00 ,  H02J9/06 ,  H03K17/163 ,  H03K17/284 ,  H03K19/01855 ,  H03K19/09429 ,  H03K19/0948 ,  H03K2017/515

Abstract: A sequential driving method for driving a switch circuit of a power converter is presented. The method has the steps of driving a switch circuit which contains a power switch, defining a driving sequence; and applying sequentially an electrical parameter to the power switch, based on the driving sequence. Defining a driving sequence includes defining a plurality of different driving levels associated with the electrical parameter and defining a plurality of time windows within a switching time period. Each time window is associated with a driving level among the plurality of driving levels.

公开(公告)号：US09923555B2

公开(公告)日：2018-03-20

申请号：US14777473

申请日：2014-03-14

Applicant: The Regents of the University of California

Inventor： Chengcheng Wang ,  Dejan Markovic

IPC: H03K17/00 ,  H03K19/177 ,  H03K19/0185 ,  H03K19/00 ,  H03K19/173 ,  H03K19/094

CPC classification number: H03K17/005 ,  H03K19/0016 ,  H03K19/018528 ,  H03K19/09429 ,  H03K19/1737 ,  H03K19/17772

Abstract: Systems and methods for power gating in logic and/or computing circuitry in accordance with embodiments of the inventions are disclosed. In one embodiment, a multiplexer for fine-grain power gating includes a first supply voltage and a second supply voltage, a plurality of inputs, a plurality of selection inputs, a selection circuitry configured to select one of the plurality of inputs, where one of the plurality of inputs is the first supply voltage and one of the selection inputs is a power gating enable input, an output inverter stage including a PMOS transistor and an NMOS transistor, where at least one input to the inverter stage is provided to the gates of the PMOS and NMOS transistors and selection of the power gating enable signal applies the first supply voltage to the gate of the PMOS transistor and places the PMOS transistor in a cutoff mode of operation.

公开(公告)号：US09595968B2

公开(公告)日：2017-03-14

申请号：US14882262

申请日：2015-10-13

Applicant: INTELLECTUAL VENTURES HOLDING 81 LLC

Inventor： Robert P. Masleid ,  Scott Pitkethly

IPC: H03K19/094 ,  H03K17/00

CPC classification number: H03K19/09429 ,  H03K17/002

Abstract: A cross point switch, in accordance with one embodiment, includes a plurality of tri-state repeaters coupled to form a plurality of multiplexers. Each set of corresponding tri-state repeaters in the plurality of multiplexers share a front end module such that delay through the cross point switch due to input capacitance is reduced as compared to conventional cross point switches.

Abstract translation: 根据一个实施例的交叉点开关包括耦合以形成多个多路复用器的多个三态中继器。 多个多路复用器中的每组相应的三态中继器共享前端模块，使得与传统的交叉点开关相比，由于输入电容而导致的交叉点开关的延迟减小。

公开(公告)号：US20160269029A1

公开(公告)日：2016-09-15

申请号：US14642887

申请日：2015-03-10

Applicant: Realtek Semiconductor Corp.

Inventor： Gerchih (Joseph) Chou ,  Chia-Liang (Leon) Lin

IPC: H03K19/0185 ,  H03K19/094

CPC classification number: H03K19/018557 ,  H03K19/09429

Abstract: In one embodiment, a method comprising receiving a logical signal; driving a source voltage at a first circuit node using a driver circuit in accordance with the logical signal; controlling an output impedance of the driver circuit using a finite state machine (FSM); transmitting the source voltage to a second circuit node via a transmission line; and terminating the second circuit node with a load circuit comprising a data detector.

Abstract translation: 在一个实施例中，一种方法包括接收逻辑信号; 使用根据逻辑信号的驱动电路在第一电路节点处驱动源极电压; 使用有限状态机（FSM）控制驱动器电路的输出阻抗; 经由传输线将源电压传输到第二电路节点; 以及用包括数据检测器的负载电路终接第二电路节点。

公开(公告)号：US20160036428A1

公开(公告)日：2016-02-04

申请号：US14777473

申请日：2014-03-14

Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

Inventor： Chengcheng WANG ,  Dejan MARKOVIC

IPC: H03K17/00 ,  H03K19/0185

CPC classification number: H03K17/005 ,  H03K19/0016 ,  H03K19/018528 ,  H03K19/09429 ,  H03K19/1737 ,  H03K19/17772

Abstract: Systems and methods for power gating in logic and/or computing circuitry in accordance with embodiments of the inventions are disclosed. In one embodiment, a multiplexer for fine-grain power gating includes a first supply voltage and a second supply voltage, a plurality of inputs, a plurality of selection inputs, a selection circuitry configured to select one of the plurality of inputs, where one of the plurality of inputs is the first supply voltage and one of the selection inputs is a power gating enable input, an output inverter stage including a PMOS transistor and an NMOS transistor, where at least one input to the inverter stage is provided to the gates of the PMOS and NMOS transistors and selection of the power gating enable signal applies the first supply voltage to the gate of the PMOS transistor and places the PMOS transistor in a cutoff mode of operation.

Abstract translation: 公开了根据本发明的实施例的用于逻辑和/或计算电路中的电源门控的系统和方法。 在一个实施例中，用于细粒度功率选通的多路复用器包括第一电源电压和第二电源电压，多个输入，多个选择输入，配置成选择多个输入之一的选择电路，其中， 所述多个输入是所述第一电源电压，并且所述选择输入中的一个是电源门控使能输入，包括PMOS晶体管和NMOS晶体管的输出反相器级，其中至少一个到所述反相器级的输入被提供给 PMOS和NMOS晶体管以及功率选通使能信号的选择将第一电源电压施加到PMOS晶体管的栅极，并将PMOS晶体管置于截止操作模式。

公开(公告)号：US20150091609A1

公开(公告)日：2015-04-02

申请号：US14088570

申请日：2013-11-25

Applicant: ARM LIMITED

Inventor： Srinivasan SRINATH ,  Ambica ASHOK ,  Fakhruddin Ali BOHRA

IPC: H03K19/017 ,  H03K19/094 ,  H03K19/00

CPC classification number: H03K19/01721 ,  G11C7/12 ,  G11C11/419 ,  H03K19/0013 ,  H03K19/09429 ,  H03K19/0963

Abstract: An integrated circuit has signal assist circuitry for assisting with pulling a signal on the signal line towards the logical low or high signal level. The signal assist circuitry comprises first and second assist circuits. The first assist circuit couples the signal line to the logical high signal level following a pullup transition of the signal and provides a floating signal level following a pulldown transition, while the second assist circuit provides the floating signal level following the pullup transition and provides the logical low signal level following the pulldown transition. By providing complementary first and second assist circuits, each circuit can be optimized for the opposite transition to achieve improved performance or power consumption.

Abstract translation: 集成电路具有信号辅助电路，用于帮助将信号线上的信号拉向逻辑低或高信号电平。 信号辅助电路包括第一和第二辅助电路。 第一辅助电路在信号的上拉转换之后将信号线耦合到逻辑高信号电平，并且在下拉转换之后提供浮动信号电平，而第二辅助电路在上拉跃迁之后提供浮动信号电平，并提供逻辑 下拉转换后的低信号电平。 通过提供互补的第一和第二辅助电路，每个电路可以针对相反的过渡进行优化，以实现改进的性能或功耗。

公开(公告)号：US20140340118A1

公开(公告)日：2014-11-20

申请号：US14364923

申请日：2012-12-11

Applicant: Soitec

Inventor： Richard Ferrant

IPC: H03K19/094 ,  H01L27/12 ,  H01L27/088

CPC classification number: H03K19/09429 ,  H01L27/0886 ,  H01L27/1203 ,  H03K19/094 ,  H03K19/0941

Abstract: The present invention relates to a tristate gate (1000, 2000) comprising an output port (1400) and at least two transistors (1200, 1300; 2200, 2300), each having at least a first and a second gate, configured such that a high-impedance value (Z) on the output port is set by controlling the threshold voltage of at least one of the transistors.

Abstract translation: 本发明涉及包括输出端口（1400）和至少两个晶体管（1200,1300,2200,2300）的三态门（1000,2000），每个至少具有第一和第二栅极，其被配置为使得 通过控制至少一个晶体管的阈值电压来设定输出端口上的高阻抗值（Z）。

公开(公告)号：US20140219036A1

公开(公告)日：2014-08-07

申请号：US14165990

申请日：2014-01-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-Hyun KIM ,  Seung-Jun BAE ,  Kyung-Soo HA

IPC: G11C7/12 ,  H03K19/094 ,  G11C7/22

CPC classification number: G11C7/22 ,  G11C7/1048 ,  G11C7/1057 ,  H03K19/00361 ,  H03K19/09429

Abstract: Provided are an equalizer and a semiconductor memory device including the same. The equalizer includes a delay circuit and an inverting circuit. The delay circuit is configured to output, in response to a select signal, one of a delay signal delaying an input signal applied to an input/output node and an inverted signal inverting the input signal. The inverting circuit is configured to invert a signal provided from the delay circuit and output the inverted signal to the input/output node. The equalizer is configured such that when the delay circuit outputs the delay signal, the equalizer operates as an inductive bias circuit amplifying the input signal and outputting the amplified input signal, and when the delay circuit outputs the inverted signal, the equalizer operates as a latch circuit storing and outputting the input signal.

Abstract translation: 提供了一种均衡器和包括该均衡器的半导体存储器件。 均衡器包括延迟电路和反相电路。 延迟电路被配置为响应于选择信号输出延迟施加到输入/输出节点的输入信号的延迟信号和反相输入信号的反相信号之一。 反相电路被配置为反转从延迟电路提供的信号并将反相信号输出到输入/输出节点。 均衡器被配置为使得当延迟电路输出延迟信号时，均衡器用作放大输入信号并输出​​放大的输入信号的感应偏置电路，并且当延迟电路输出反相信号时，均衡器作为锁存器 电路存储和输出输入信号。

公开(公告)号：US08476947B2

公开(公告)日：2013-07-02

申请号：US13295875

申请日：2011-11-14

Applicant: John Henry Bui ,  Lay Hock Khoo ,  Khai Nguyen ,  Chiakang Sung ,  Ket Chiew Sia

Inventor： John Henry Bui ,  Lay Hock Khoo ,  Khai Nguyen ,  Chiakang Sung ,  Ket Chiew Sia

IPC: H03K3/017

CPC classification number: H03K5/1565 ,  H03K19/018592 ,  H03K19/09429

Abstract: Integrated circuits with clock generation and distribution circuitry are provided. Integrated circuits may include phase-locked loops configured to generate multiple clock signals that are delayed versions of one another. The clocks signal may be distributed to various regions on an integrated circuit using serially connected clock buffer blocks. Each buffer block may include bidirectional pairs of buffer circuits coupled in parallel. Each buffer circuit may have a first input configured to receive an input clock signal, an output at which a corrected version of the input clock signal is provided (e.g., an output at which an output clock signal with desired duty cycle is provided), a second input that receives a first delayed clock signal for setting the desired duty cycle for the output clock signal, and a third input that receives a second delayed clock signal that is high at least when the first delayed clock signal rises high.

公开(公告)号：US08466752B2

公开(公告)日：2013-06-18

申请号：US13100656

申请日：2011-05-04

Applicant: Kristopher Kevin Kaufman ,  John Wayne Simmons

Inventor： Kristopher Kevin Kaufman ,  John Wayne Simmons

IPC: H03B5/36 ,  H03B5/02

CPC classification number: H03K3/36 ,  H03B5/02 ,  H03B5/1206 ,  H03B5/1228 ,  H03B5/364 ,  H03B2200/0012 ,  H03B2200/0026 ,  H03B2200/0046 ,  H03F3/72 ,  H03K19/09429

Abstract: In accordance with some embodiments of the present disclosure, an oscillator circuit comprises, a first pad associated with a first terminal of an oscillator and a second pad associated with a second terminal of the oscillator. The oscillator is configured to generate an oscillating signal and communicate the oscillating signal from the second terminal to a clock distributor coupled to the second pad. The oscillator circuit further comprises an oscillator gain element comprising an output node coupled to the first pad and an input node coupled to the second pad. The oscillator circuit also comprises a digital-to-analog converter (DAC) coupled to the first pad. The oscillator circuit additionally comprises a switching circuit coupled to the gain element. The switching circuit is configured to enable the gain element when the oscillator comprises a resonator and disable the gain element when the oscillator comprises a voltage controlled oscillating module.