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公开(公告)号：US12095458B2
公开(公告)日：2024-09-17
申请号：US17825378
申请日：2022-05-26
IPC分类号： H03K19/0185 , H03K19/017 , H03K19/094 , H03K19/20
CPC分类号： H03K19/01855 , H03K19/01742 , H03K19/0941 , H03K19/20
摘要： A method, implemented in a serializer for quarter rate serialization, is disclosed. The method includes receiving a plurality of in-phase and quarter-phase clock signals defining a quarter phase clock. The method includes receiving a quarter rate data input and sequentially outputting data in accordance with the quarter phase clock. The method includes receiving at least one data input from amongst the quarter rate input and outputting a first logical output in accordance with the in-phase clock signal and the quarter-phase clock signal. The method includes receiving said at least one data input and outputting a second logical output in accordance a complementary in-phase clock signal and a complementary quarter-phase clock signal. The method includes outputting, an output associated with the branch.
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公开(公告)号：US10804904B1
公开(公告)日：2020-10-13
申请号：US16725580
申请日：2019-12-23
摘要： A multi-lane transmitter and method of detecting a sync loss are provided. The method includes generating a high-speed clock signal and a sync reset signal synchronized to the high-speed clock signal. A sync loss pulse is generated based on the high-speed clock signal, and the sync loss pulse is provided to each of plural serializer circuits. Each serializer circuit generates a sampled sync loss signal by sampling the sync loss pulse in accordance with a parallel clock signal, and a Boolean value is assigned to the sampled sync loss signal and output. A logic block detects a sync loss when the sampled sync loss signal of any serializer circuit is out of sync from the sync loss pulse based on the Boolean value.
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公开(公告)号：US11979263B2
公开(公告)日：2024-05-07
申请号：US17872258
申请日：2022-07-25
CPC分类号： H04L25/03878 , H04B3/06 , H04B17/14
摘要： A wire-line transceiver is configured to perform a serial loop back test. The wire-line transceiver includes an on-chip transmitter, an on-chip receiver and a fractional feed forward equalizer circuit (fractional FFE circuit) in a serial loop back line path between the on-chip transmitter and the on-chip receiver. The fractional FFE circuit is configured to induce a delay one of less than one symbol time of data, for enhancing an eye opening from the serial loop back line during the serial loop back test, compared to a situation where the fractional FFE circuit is not present or is not used.
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4.发明公开公开(公告)号：US20230324937A1
公开(公告)日：2023-10-12
申请号：US17829690
申请日：2022-06-01
发明人： Ankur Ghosh , Praveen Rathee , Sumanth Chakkirala , Tamal Das
IPC分类号： G05F1/56
CPC分类号： G05F1/56 , H03K19/017509
摘要： Methods and systems for selecting voltage for a substrate connection of a bypass switch include a bulk voltage generation circuit coupled externally to the regulator. The bulk voltage generation circuit is configured to control selection of a voltage from among an Input/Output (I/O) supply voltage and a core supply voltage for a substrate connection of a bypass switch of the regulator. The bulk voltage generation circuit is configured to select the voltage for the substrate connection of the bypass switch based on a mode of operation of the regulator and at least one of a presence or an arrival sequence of the I/O supply voltage and the core supply voltage.
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5.发明授权公开(公告)号：US11303278B1
公开(公告)日：2022-04-12
申请号：US17222349
申请日：2021-04-05
IPC分类号： H03K3/00 , H03K19/0175 , H03K19/0185 , H03L5/00 , H03K3/356
摘要： The present disclosure relates to a circuit for level shifting of a data voltage from a transmitter. The circuit comprises an inverter logic. The inverter logic comprises a first transistor and a second transistor. The first transistor is connected to a source voltage and the second transistor is connected to ground. A capacitor is connected to an input of the first transistor and configured to drive the first transistor. The capacitor is configured to charge to a charged voltage equivalent to a difference between the source voltage and the data voltage. The second transistor is configured to be driven by the data voltage, thereby level shifting a level of the data voltage to a level of the source voltage.
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公开(公告)号：US10892775B1
公开(公告)日：2021-01-12
申请号：US16796232
申请日：2020-02-20
摘要： Various example embodiments relate to unifying a plurality of parallel interfaces. A transmitting apparatus configured to serialize parallel bits implements a dynamic divider circuit for loading varying parallel bits into the transmitting apparatus. An input clock generator is configured to generate a desired and/or predefined clock frequency. The dynamic divider circuit receives the desired and/or predefined clock frequency and generates a parallel clock frequency by dividing the desired and/or predefined clock frequency based on a variable division input. Number of parallel bits loaded into the transmitting apparatus is based on the generated parallel clock frequency. Further, a shift register generates a bit stream from the parallel bits loaded into the shift register and the generated bit stream is converted to serial bit by a multiplexer.
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公开(公告)号：US11256286B1
公开(公告)日：2022-02-22
申请号：US17222186
申请日：2021-04-05
摘要： The electronic circuit for multiphase clock skew calibration of at least one example embodiment provides a novel low power solution to detect clock skew errors with very high accuracy, of the order of a few femto seconds, and corrects clock skew errors and decreases and/or minimizes high frequency jitter in a data path of the electronic circuit.
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公开(公告)号：US11196420B1
公开(公告)日：2021-12-07
申请号：US17026487
申请日：2020-09-21
发明人： Tamal Das , Ankur Ghosh
IPC分类号： H03K19/0185 , H03K3/356
摘要： A level shifter includes main and auxiliary level shifters, a switch circuit and a hold circuit. The main level shifter includes NMOS and PMOS transistors in a Differential to Single Ended (D2S) structure. The auxiliary level shifter is connected to an output of the main level shifter and includes NMOS and PMOS transistors. Each of the main and auxiliary level shifters includes internal nodes. The switch circuit settles first nodes of the internal nodes to values to support high speed data transmission, and the hold circuit holds second nodes of the internal nodes to a certain value during low frequency operation. The level shifter receives a serial stream of binary values of core supply voltage, converts the serial stream of binary values from the core supply voltage to an input/output (I/O) voltage, and outputs the serial stream of binary values of the input/output (I/O) voltage.
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公开(公告)号：US11611426B2
公开(公告)日：2023-03-21
申请号：US17470334
申请日：2021-09-09
摘要： A multi-lane transmitting apparatus includes lanes, and each lane includes a serializer circuit to convert parallel bits to serial bits. A clock signal generator generates a first clock signal having phases. A deserializer circuit converts serial bits to parallel bits. A Built-In Self-Test (BIST) circuit includes a signal generator circuit for generating a signal having bits in a defined pattern. A comparator circuit compares a pattern of bits of an output signal with the defined pattern. A BIST lane circuit monitors a status of the lanes. A BIST central circuit receives the status and determines if a number of lanes having an unmatched status is less than a threshold value. A phase extrapolator circuit adjusts a phase of the first clock signal when the number of the lanes is less than the threshold value.
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公开(公告)号：US20220329405A1
公开(公告)日：2022-10-13
申请号：US17470334
申请日：2021-09-09
IPC分类号： H04L7/00
摘要： A multi-lane transmitting apparatus includes lanes, and each lane includes a serializer circuit to convert parallel bits to serial bits. A clock signal generator generates a first clock signal having phases. A deserializer circuit converts serial bits to parallel bits. A Built-In Self-Test (BIST) circuit includes a signal generator circuit for generating a signal having bits in a defined pattern. A comparator circuit compares a pattern of bits of an output signal with the defined pattern. A BIST lane circuit monitors a status of the lanes. A BIST central circuit receives the status and determines if a number of lanes having an unmatched status is less than a threshold value. A phase extrapolator circuit adjusts a phase of the first clock signal when the number of the lanes is less than the threshold value.
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