公开(公告)号：US08873689B2

公开(公告)日：2014-10-28

申请号：US13564758

申请日：2012-08-02

Applicant: Tao Wen Chung ,  Chan-Hong Chern ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Yuwen Swei

Inventor： Tao Wen Chung ,  Chan-Hong Chern ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Yuwen Swei

IPC: H04L7/00

CPC classification number: H03K5/135 ,  H03H11/20 ,  H03K2005/00052 ,  H04L7/0029

Abstract: A phase interpolator for a CDR circuit produces an output clock having level transitions between the level transitions on two input clocks. The input clocks drive cross-coupled differential amplifiers with an output that can be varied in phase by variable current throttling or steering, according to an input control value. The differential amplifiers produce an output signal with a transition spanning a time between the start of a transition on the leading input clock up to the end of the transition on the lagging input clock. The output clock is linear so long as the transitions on the two input clocks overlap. Active integrators each having an amplifier with a series resistance and capacitive feedback path are coupled to each input to the cross-coupled differential amplifiers, which enhances overlap of the input clock rise times and improves the linearity of the interpolated output signal.

Abstract translation: 用于CDR电路的相位插值器产生具有在两个输入时钟上的电平转换之间的电平转换的输出时钟。 输入时钟驱动交叉耦合差分放大器，输出可根据输入控制值通过可变电流节流或转向相位变化。 差分放大器产生一个输出信号，该输出信号跨越在引导输入时钟之间的转换开始到延迟输入时钟转换结束之间的时间。 输出时钟是线性的，只要两个输入时钟的转换重叠即可。 每个具有串联电阻和电容反馈路径的放大器的积分器耦合到交叉耦合差分放大器的每个输入，这增强了输入时钟上升时间的重叠，并提高了内插输出信号的线性度。

公开(公告)号：US08847652B2

公开(公告)日：2014-09-30

申请号：US13558670

申请日：2012-07-26

Applicant: Chan-Hong Chern ,  Tao Wen Chung ,  Chih-Chang Lin ,  Ming-Chieh Huang ,  Tsung-Ching Huang ,  Fu-Lung Hsueh

Inventor： Chan-Hong Chern ,  Tao Wen Chung ,  Chih-Chang Lin ,  Ming-Chieh Huang ,  Tsung-Ching Huang ,  Fu-Lung Hsueh

IPC: G06F1/10 ,  H03K5/15

CPC classification number: G06F1/10 ,  H03B5/12 ,  H03B5/32 ,  H03K5/15

Abstract: The present disclosure relates to a resonant clock system having a driver component, a clock load capacitor, and a reconfigurable inductor array. The driver component generates a driven input signal. The clock load capacitor is configured to receive the driven input signal. The inductor array is configured to have an effective inductance according to a selected frequency. The inductor array also generates a resonant signal at the selected frequency using the effective inductance.

Abstract translation: 本公开涉及具有驱动器部件，时钟负载电容器和可重构电感器阵列的谐振时钟系统。 驱动器组件产生驱动输入信号。 时钟负载电容器被配置为接收驱动输入信号。 电感器阵列被配置为具有根据选定频率的有效电感。 电感器阵列还使用有效电感在选定频率处产生谐振信号。

公开(公告)号：US08709684B2

公开(公告)日：2014-04-29

申请号：US13562436

申请日：2012-07-31

Applicant: Chan-Hong Chern ,  Tao Wen Chung ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Tsung-Ching (Jim) Huang ,  Fu-Lung Hsueh

Inventor： Chan-Hong Chern ,  Tao Wen Chung ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Tsung-Ching (Jim) Huang ,  Fu-Lung Hsueh

IPC: G03F1/68

CPC classification number: G03F7/70466 ,  G03F7/70433 ,  G06F17/5077

Abstract: Some aspects of the present disclosure provide for a method of automatically balancing mask misalignment for multiple patterning layers to minimize the consequences of mask misalignment. In some embodiments, the method defines a routing grid for one or more double patterning layers within an IC layout. The routing grid has a plurality of vertical grid lines extending along a first direction and a plurality of horizontal grid lines extending along a second, orthogonal direction. Alternating lines of the routing grid in a given direction (e.g., the horizontal and vertical direction) are assigned different colors. Shapes on the double patterning layers are then routed along the routing grid in a manner that alternates between different colored grid lines. By routing in such a manner, variations in capacitive coupling caused by mask misalignment are reduced.

Abstract translation: 本公开的一些方面提供了一种自动平衡多个图案化层的掩模未对准的方法，以最小化掩模未对准的后果。 在一些实施例中，该方法定义了IC布局内的一个或多个双图案化层的布线网格。 路由网格具有沿着第一方向延伸的多个垂直网格线和沿着第二正交方向延伸的多个水平网格线。 在给定方向（例如，水平和垂直方向）上布线网格的交替线被分配不同的颜色。 然后双重图案化层上的形状沿着布线网格以不同颜色的网格线之间交替的方式布线。 通过以这种方式进行布线，减少了由掩模未对准引起的电容耦合的变化。

公开(公告)号：US20140015611A1

公开(公告)日：2014-01-16

申请号：US13547101

申请日：2012-07-12

Applicant: Tao Wen CHUNG ,  Chan-Hong CHERN ,  Ming-Chieh HUANG ,  Chih-Chang LIN ,  Yuwen SWEI

Inventor： Tao Wen CHUNG ,  Chan-Hong CHERN ,  Ming-Chieh HUANG ,  Chih-Chang LIN ,  Yuwen SWEI

IPC: H03F3/04

CPC classification number: G01R31/2621

Abstract: A circuit has a first circuit module including a first resistor and first and second transistors coupled in parallel with the first resistor. The first resistor and the first and second transistors are coupled together at a first node. An equivalent resistance across the first circuit module increases as a voltage of the first node is increased from a first voltage to a second voltage, and the equivalent resistance across the first circuit module decreases as the voltage of the first node is increased from the second voltage to a third voltage.

Abstract translation: 电路具有包括第一电阻器和与第一电阻器并联耦合的第一和第二晶体管的第一电路模块。 第一电阻器和第一和第二晶体管在第一节点耦合在一起。 当第一节点的电压从第一电压增加到第二电压时，跨第一电路模块的等效电阻增加，并且第一电路模块上的等效电阻随着第一节点的电压从第二电压增加而减小 到第三电压。

公开(公告)号：US20140002332A1

公开(公告)日：2014-01-02

申请号：US13539181

申请日：2012-06-29

Applicant: Tsung-Ching HUANG ,  Chan-Hong CHERN ,  Tao Wen CHUNG ,  Ming-Chieh HUANG ,  Chih-Chang LIN

Inventor： Tsung-Ching HUANG ,  Chan-Hong CHERN ,  Tao Wen CHUNG ,  Ming-Chieh HUANG ,  Chih-Chang LIN

IPC: G09G3/32

CPC classification number: G09G3/3233 ,  G09G3/3406 ,  G09G2300/0809 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2320/0233 ,  G09G2320/0295 ,  G09G2320/045 ,  G09G2330/028

Abstract: A current value of a first pixel and/or a current value of a second pixel of a display are adjusted until a value of a current difference is acceptable. The current value of the first pixel corresponds to a brightness level of the first pixel. The current value of the second pixel corresponds to a brightness level of the second pixel. Adjusting the current value of the first pixel involves adjusting a threshold voltage value of a transistor of the first pixel. Adjusting the current value of the second pixel involves adjusting a threshold voltage value of a transistor of the second pixel.

Abstract translation: 调整显示器的第二像素的第一像素的当前值和/或当前值，直到电流差的值是可接受的。 第一像素的当前值对应于第一像素的亮度级。 第二像素的当前值对应于第二像素的亮度级。 调整第一像素的当前值包括调整第一像素的晶体管的阈值电压值。 调整第二像素的当前值包括调整第二像素的晶体管的阈值电压值。

公开(公告)号：US08614604B2

公开(公告)日：2013-12-24

申请号：US13312228

申请日：2011-12-06

Applicant: Tao-Wen Chung ,  Chan-Hong Chern ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Yuwen Swei

Inventor： Tao-Wen Chung ,  Chan-Hong Chern ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Yuwen Swei

IPC: H03F3/68

CPC classification number: H03F3/68 ,  H03F1/42 ,  H03F3/191 ,  H03F3/195 ,  H03F3/45183 ,  H03F2200/36 ,  H03F2200/405 ,  H03F2203/45638 ,  H03F2203/45702

Abstract: A method of sharing inductors for inductive peaking of an amplifier having at least two stages includes calculating a single stage inductance of a single stage of the at least two stages for inductive peaking in order to have a stable impulse response. A shared inductance is calculated for inductive peaking by dividing the single stage inductance by a number of stages of the at least two stages. At least two inductors having the shared inductance are shared among the at least two stages for inductive peaking.

Abstract translation: 共享用于具有至少两级的放大器的感应峰化的电感器的方法包括计算用于感应峰值的至少两级的单级的单级电感，以便具有稳定的脉冲响应。 通过将单级电感除以至少两级的多个级来计算感应峰值的共享电感。 具有共享电感的至少两个电感器在用于感应峰化的至少两个级中共享。

公开(公告)号：US08570068B2

公开(公告)日：2013-10-29

申请号：US12768899

申请日：2010-04-28

Applicant: Chan-Hong Chern ,  Fu-Lung Hsueh ,  Ming-Chieh Huang ,  Bryan Sheffield ,  Chih-Chang Lin

Inventor： Chan-Hong Chern ,  Fu-Lung Hsueh ,  Ming-Chieh Huang ,  Bryan Sheffield ,  Chih-Chang Lin

IPC: H03K19/0175

CPC classification number: H03K19/01855 ,  H03K3/012 ,  H03K3/356008 ,  H03K3/35625 ,  H03K19/0016 ,  H03K19/0963

Abstract: A circuit includes an operational PMOS transistor of a logic gate driver. A control circuit is configured to turn off the operational PMOS transistor during a standby mode. The circuit also includes a sacrificial PMOS transistor coupled to an output node. The operational PMOS transistor is coupled to the output node. The sacrificial PMOS transistor is configured to keep the output node at a logical 1 during the standby mode.

Abstract translation: 电路包括逻辑门驱动器的操作PMOS晶体管。 控制电路被配置为在待机模式期间关闭操作PMOS晶体管。 电路还包括耦合到输出节点的牺牲PMOS晶体管。 操作PMOS晶体管耦合到输出节点。 牺牲PMOS晶体管被配置为在待机模式期间将输出节点保持在逻辑1。

公开(公告)号：US20130127433A1

公开(公告)日：2013-05-23

申请号：US13744037

申请日：2013-01-17

Applicant: Chan-Hong CHERN ,  Tzu Ching CHANG ,  Min-Shueh YUAN ,  Yuwen SWEI ,  Chih-Chang LIN ,  Chiang PU ,  Ming-Chieh HUANG ,  Kuoyuan HSU

Inventor： Chan-Hong CHERN ,  Tzu Ching CHANG ,  Min-Shueh YUAN ,  Yuwen SWEI ,  Chih-Chang LIN ,  Chiang PU ,  Ming-Chieh HUANG ,  Kuoyuan HSU

IPC: G05F1/44

CPC classification number: H02M3/158 ,  G05F1/44 ,  G05F1/56

Abstract: A method of operating a voltage regulator circuit includes generating a control signal by an amplifier of the voltage regulator circuit. The control signal is generated based on a reference signal at an inverting input of the amplifier and a feedback signal at a non-inverting input of the amplifier. A driving current flowing toward an output node of the voltage regulator circuit is generated by a driver responsive to the control signal, and the driver is coupled between a first power node and the output node. The feedback signal is generated responsive to a voltage level at the output node. A transistor, coupled between the output node and a second power node, is caused to operate in saturation mode during a period while the voltage regulator circuit is operating.

Abstract translation: 一种操作电压调节器电路的方法包括由稳压器电路的放大器产生控制信号。 控制信号基于放大器的反相输入处的参考信号和放大器的非反相输入端的反馈信号而产生。 通过响应于控制信号的驱动器产生朝向电压调节器电路的输出节点流动的驱动电流，并且驱动器耦合在第一功率节点和输出节点之间。 响应于输出节点处的电压电平产生反馈信号。 耦合在输出节点和第二功率节点之间的晶体管在电压调节器电路工作期间的一段时间内使其工作在饱和模式。

公开(公告)号：US20130099767A1

公开(公告)日：2013-04-25

申请号：US13278742

申请日：2011-10-21

Applicant: Ming-Chieh HUANG ,  Tao Wen CHUNG ,  Chan-Hong CHERN ,  Chih-Chang LIN ,  Yuwen SWEI ,  Chiang PU

Inventor： Ming-Chieh HUANG ,  Tao Wen CHUNG ,  Chan-Hong CHERN ,  Chih-Chang LIN ,  Yuwen SWEI ,  Chiang PU

IPC: G05F3/02

CPC classification number: H03H11/44 ,  H01S5/0427 ,  H04B10/504

Abstract: A driver includes a first driver stage having at least one input node and at least one first output node. The first driver stage includes a T-coil structure that is disposed adjacent to the at least one first output node. The T-coil structure includes a first set of inductors each being operable to provide a first inductance. A second set of inductors are electrically coupled with the first set of inductors in a parallel fashion. The second set of inductors each are operable to provide a second inductance. A second driver stage is electrically coupled with the first driver stage.

Abstract translation: 驱动器包括具有至少一个输入节点和至少一个第一输出节点的第一驱动器级。 第一驱动级包括邻近于至少一个第一输出节点设置的T型线圈结构。 T型线圈结构包括第一组电感器，每个电感器可操作以提供第一电感。 第二组电感器以并行方式与第一组电感器电耦合。 第二组电感器可操作以提供第二电感。 第二驱动级与第一驱动器级电耦合。

公开(公告)号：US08368437B2

公开(公告)日：2013-02-05

申请号：US13039095

申请日：2011-03-02

Applicant: Ming-Chieh Huang ,  Chih-Chang Lin ,  Tao Wen Chung ,  Chan-Hong Chern

Inventor： Ming-Chieh Huang ,  Chih-Chang Lin ,  Tao Wen Chung ,  Chan-Hong Chern

IPC: H03L7/06

CPC classification number: H03L7/0896 ,  H03L7/089 ,  H03L7/0893

Abstract: A phase locked loop (PLL) includes a voltage controlled oscillator (VCO) configured to supply an output signal. A phase frequency detector (PFD) is configured to receive a reference frequency signal and to provide a first control signal. A first charge pump is configured to receive the first control signal and to provide a first voltage signal in order to control the VCO. A second charge pump is configured to receive the first control signal and to provide a second voltage signal. A comparator is configured to receive a reference voltage signal, to compare the reference voltage signal and the second voltage signal, and to provide a second control signal. The PFD is configured to adjust at least one side slope of the first control signal based on the second control signal.

Abstract translation: 锁相环（PLL）包括被配置为提供输出信号的压控振荡器（VCO）。 相位频率检测器（PFD）被配置为接收参考频率信号并提供第一控制信号。 第一电荷泵被配置为接收第一控制信号并提供第一电压信号以便控制VCO。 第二电荷泵被配置为接收第一控制信号并提供第二电压信号。 比较器被配置为接收参考电压信号，以比较参考电压信号和第二电压信号，并提供第二控制信号。 PFD被配置为基于第二控制信号来调整第一控制信号的至少一个侧斜率。