公开(公告)号：US09134360B2

公开(公告)日：2015-09-15

申请号：US13547101

申请日：2012-07-12

Applicant: Tao Wen Chung ,  Chan-Hong Chern ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Yuwen Swei

Inventor： Tao Wen Chung ,  Chan-Hong Chern ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Yuwen Swei

IPC: H03L5/00 ,  G01R31/26

CPC classification number: G01R31/2621

Abstract: A circuit has a first circuit module including a first resistor and first and second transistors coupled in parallel with the first resistor. The first resistor and the first and second transistors are coupled together at a first node. An equivalent resistance across the first circuit module increases as a voltage of the first node is increased from a first voltage to a second voltage, and the equivalent resistance across the first circuit module decreases as the voltage of the first node is increased from the second voltage to a third voltage.

Abstract translation: 电路具有包括第一电阻器和与第一电阻器并联耦合的第一和第二晶体管的第一电路模块。 第一电阻器和第一和第二晶体管在第一节点耦合在一起。 当第一节点的电压从第一电压增加到第二电压时，跨第一电路模块的等效电阻增加，并且第一电路模块上的等效电阻随着第一节点的电压从第二电压增加而减小 到第三电压。

公开(公告)号：US08896352B2

公开(公告)日：2014-11-25

申请号：US13278742

申请日：2011-10-21

Applicant: Ming-Chieh Huang ,  Tao Wen Chung ,  Chan-Hong Chern ,  Chih-Chang Lin ,  Yuwen Swei ,  Chiang Pu

Inventor： Ming-Chieh Huang ,  Tao Wen Chung ,  Chan-Hong Chern ,  Chih-Chang Lin ,  Yuwen Swei ,  Chiang Pu

IPC: H03K3/00

CPC classification number: H03H11/44 ,  H01S5/0427 ,  H04B10/504

Abstract: A driver includes a first driver stage having at least one input node and at least one first output node. The first driver stage includes a T-coil structure that is disposed adjacent to the at least one first output node. The T-coil structure includes a first set of inductors each being operable to provide a first inductance. A second set of inductors are electrically coupled with the first set of inductors in a parallel fashion. The second set of inductors each are operable to provide a second inductance. A second driver stage is electrically coupled with the first driver stage.

Abstract translation: 驱动器包括具有至少一个输入节点和至少一个第一输出节点的第一驱动器级。 第一驱动级包括邻近于至少一个第一输出节点设置的T型线圈结构。 T型线圈结构包括第一组电感器，每个电感器可操作以提供第一电感。 第二组电感器以并行方式与第一组电感器电耦合。 第二组电感器可操作以提供第二电感。 第二驱动级与第一驱动器级电耦合。

公开(公告)号：US08816732B2

公开(公告)日：2014-08-26

申请号：US13530136

申请日：2012-06-22

Applicant: Chan-Hong Chern ,  Tao Wen Chung ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Tsung-Ching Huang ,  Fu-Lung Hsueh

Inventor： Chan-Hong Chern ,  Tao Wen Chung ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Tsung-Ching Huang ,  Fu-Lung Hsueh

IPC: H03L7/06

CPC classification number: H03L7/103 ,  H03L7/097 ,  H03L7/0995 ,  H03L7/1072 ,  H03L7/18 ,  H03L2207/06

Abstract: A circuit includes a capacitive-load voltage controlled oscillator having an input configured to receive a first input signal and an output configured to output an oscillating output signal. A calibration circuit is coupled to the voltage controlled oscillator and is configured to output one or more control signals to the capacitive-load voltage controlled oscillator for adjusting a frequency of the oscillating output signal. The calibration circuit is configured to output the one or more control signals in response to a comparison of an input voltage to at least one reference voltage.

Abstract translation: 电路包括电容负载压控振荡器，其具有被配置为接收第一输入信号的输入和被配置为输出振荡输出信号的输出。 校准电路耦合到压控振荡器，并被配置为将一个或多个控制信号输出到电容负载压控振荡器，用于调整振荡输出信号的频率。 校准电路被配置为响应于输入电压与至少一个参考电压的比较而输出一个或多个控制信号。

公开(公告)号：US08750070B2

公开(公告)日：2014-06-10

申请号：US13759791

申请日：2013-02-05

Applicant: Ming-Chieh Huang ,  Kuoyuan (Peter) Hsu

Inventor： Ming-Chieh Huang ,  Kuoyuan (Peter) Hsu

IPC: G11C5/14 ,  G11C7/12

CPC classification number: G11C5/14 ,  G11C5/147 ,  G11C7/12 ,  G11C7/14 ,  G11C11/4094 ,  G11C11/4099

Abstract: A memory circuit including at least one memory cell connected to a bit line. The memory circuit further includes a means for providing a bit line reference voltage VBLref to the bit line. A VBLref/VDD ratio of the bit line reference voltage VBLref to a power voltage VDD is adjustable corresponding to a change of the power voltage VDD, and the VBLref/VDD ratio ranges from about 0.4 to about 0.53.

Abstract translation: 一种存储器电路，包括连接到位线的至少一个存储单元。 存储电路还包括用于向位线提供位线参考电压VBLref的装置。 位线参考电压VBLref与电源电压VDD的VBLref / VDD比可根据电源电压VDD的变化进行调整，VBLref / VDD比范围为约0.4至约0.53。

公开(公告)号：US20140038085A1

公开(公告)日：2014-02-06

申请号：US13562436

申请日：2012-07-31

Applicant: Chan-Hong Chern ,  Tao Wen Chung ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Tsung-Ching (Jim) Huang ,  Fu-Lung Hsueh

Inventor： Chan-Hong Chern ,  Tao Wen Chung ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Tsung-Ching (Jim) Huang ,  Fu-Lung Hsueh

IPC: G06F17/50 ,  G03F1/68

CPC classification number: G03F7/70466 ,  G03F7/70433 ,  G06F17/5077

Abstract: Some aspects of the present disclosure provide for a method of automatically balancing mask misalignment for multiple patterning layers to minimize the consequences of mask misalignment. In some embodiments, the method defines a routing grid for one or more double patterning layers within an IC layout. The routing grid has a plurality of vertical grid lines extending along a first direction and a plurality of horizontal grid lines extending along a second, orthogonal direction. Alternating lines of the routing grid in a given direction (e.g., the horizontal and vertical direction) are assigned different colors. Shapes on the double patterning layers are then routed along the routing grid in a manner that alternates between different colored grid lines. By routing in such a manner, variations in capacitive coupling caused by mask misalignment are reduced.

Abstract translation: 本公开的一些方面提供了一种自动平衡多个图案化层的掩模未对准的方法，以最小化掩模未对准的后果。 在一些实施例中，该方法定义了IC布局内的一个或多个双图案化层的布线网格。 路由网格具有沿着第一方向延伸的多个垂直网格线和沿着第二正交方向延伸的多个水平网格线。 在给定方向（例如，水平和垂直方向）上布线网格的交替线被分配不同的颜色。 然后双重图案化层上的形状沿着布线网格以不同颜色的网格线之间交替的方式布线。 通过以这种方式进行布线，减少了由掩模未对准引起的电容耦合的变化。

公开(公告)号：US20140028407A1

公开(公告)日：2014-01-30

申请号：US13558670

申请日：2012-07-26

Applicant: Chan-Hong Chern ,  Tao Wen Chung ,  Chih-Chang Lin ,  Ming-Chieh Huang ,  Tsung-Ching Huang ,  Fu-Lung Hsueh

Inventor： Chan-Hong Chern ,  Tao Wen Chung ,  Chih-Chang Lin ,  Ming-Chieh Huang ,  Tsung-Ching Huang ,  Fu-Lung Hsueh

IPC: H03B5/12

CPC classification number: G06F1/10 ,  H03B5/12 ,  H03B5/32 ,  H03K5/15

Abstract: The present disclosure relates to a resonant clock system having a driver component, a clock load capacitor, and a reconfigurable inductor array. The driver component generates a driven input signal. The clock load capacitor is configured to receive the driven input signal. The inductor array is configured to have an effective inductance according to a selected frequency. The inductor array also generates a resonant signal at the selected frequency using the effective inductance.

Abstract translation: 本公开涉及具有驱动器部件，时钟负载电容器和可重构电感器阵列的谐振时钟系统。 驱动器组件产生驱动输入信号。 时钟负载电容器被配置为接收驱动输入信号。 电感器阵列被配置为具有根据选定频率的有效电感。 电感器阵列还使用有效电感在选定频率处产生谐振信号。

公开(公告)号：US08610421B2

公开(公告)日：2013-12-17

申请号：US12976504

申请日：2010-12-22

Applicant: Ming-Chieh Huang ,  Chan-Hong Chern ,  Chih-Chang Lin

Inventor： Ming-Chieh Huang ,  Chan-Hong Chern ,  Chih-Chang Lin

IPC: G05F1/648

CPC classification number: G05F1/648 ,  G11C5/147 ,  H02M3/158

Abstract: A current generator includes an op-amp having a negative terminal arranged to be coupled to an input voltage, a resistance selection circuit having at least one tunable resistor connected with each other, and at least one power transistor. A gate of the at least one power transistor is coupled to an output of the op-amp, and a drain of the at least one power transistor is coupled to the at least one tunable resistor or a load. The resistance selection circuit is configured to select a node of the at least one tunable resistor based on the input voltage for coupling from a positive terminal of the op-amp. The at least one tunable resistor is configured to adjust a resistance setting to control a current level of the current generator based on a power supply voltage or a current of a reference resistor.

Abstract translation: 电流发生器包括具有布置为耦合到输入电压的负极端子的运算放大器，具有彼此连接的至少一个可调电阻器的电阻选择电路和至少一个功率晶体管。 所述至少一个功率晶体管的栅极耦合到所述运算放大器的输出，并且所述至少一个功率晶体管的漏极耦合到所述至少一个可调电阻器或负载。 电阻选择电路被配置为基于用于从运算放大器的正极端子耦合的输入电压来选择至少一个可调电阻器的节点。 所述至少一个可调电阻器被配置为基于电源电压或参考电阻器的电流来调整电阻设置以控制电流发生器的电流水平。

公开(公告)号：US20130121396A1

公开(公告)日：2013-05-16

申请号：US13293513

申请日：2011-11-10

Applicant: Ming-Chieh HUANG ,  Jing Jing CHEN ,  Chan-Hong CHERN ,  Tao Wen CHUNG ,  Chih-Chang LIN ,  Yuwen SWEI

Inventor： Ming-Chieh HUANG ,  Jing Jing CHEN ,  Chan-Hong CHERN ,  Tao Wen CHUNG ,  Chih-Chang LIN ,  Yuwen SWEI

IPC: H04L27/01

CPC classification number: H04L25/03057 ,  H04L2025/0349 ,  H04L2025/03566 ,  H04L2025/03617 ,  H04L2025/03687

Abstract: A Decision Feedback Equalizer (DFE) with programmable taps includes a summer configured to receive a DFE input signal. Delay elements are coupled to the summer. The delay elements are connected in series. Each delay element provides a respective delayed signal of an input signal to the delay element. A weight generator is configured to provide tap weights. The DFE is configured to multiply each tap weight to the respective delayed signal from the respective delay element to provide tap outputs. Each tap output is selectively enabled to be added to the summer or disabled based on a first comparison of a first threshold value and each impulse response or each tap weight corresponding to the respective tap output, where the impulse response is the DFE input signal in response to a pulse signal transmitted through a channel.

Abstract translation: 具有可编程抽头的判决反馈均衡器（DFE）包括一个加法器，用于接收DFE输入信号。 延迟元素与夏天相结合。 延迟元件串联连接。 每个延迟元件向延迟元件提供输入信号的相应延迟信号。 重量发生器被配置成提供抽头重量。 DFE被配置为将每个抽头权重乘以来自相应延迟元件的相应延迟信号以提供抽头输出。 基于第一阈值和对应于各抽头输出的每个脉冲响应或每个抽头权重的第一比较，每个抽头输出被选择性地被加到加法器或禁止中，其中脉冲响应是响应中的DFE输入信号 通过通道传输的脉冲信号。

公开(公告)号：US20130120051A1

公开(公告)日：2013-05-16

申请号：US13737624

申请日：2013-01-09

Applicant: Chiang PU ,  Ming-Chieh HUANG ,  Chan-Hong CHERN

Inventor： Chiang PU ,  Ming-Chieh HUANG ,  Chan-Hong CHERN

IPC: G05F1/10

CPC classification number: G05F1/10 ,  G11C7/22 ,  G11C7/222 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40626 ,  G11C2211/4065

Abstract: A circuit includes a comparator, a first circuit, and a second circuit. The comparator includes a first input node, a second input node, and an output node. The first circuit is configured to generate a temperature-dependent reference current at the second input node of the comparator. The second circuit is coupled with the second input node of the comparator. The second circuit is configured to increase a voltage level at the second input node of the comparator in response to the temperature-dependent reference current when a signal at the output node of the comparator indicates a first comparison result, and decrease the voltage level at the second input node of the comparator when the signal at the output node of the comparator indicates a second comparison result.

Abstract translation: 电路包括比较器，第一电路和第二电路。 比较器包括第一输入节点，第二输入节点和输出节点。 第一电路被配置为在比较器的第二输入节点处产生与温度相关的参考电流。 第二电路与比较器的第二输入节点耦合。 第二电路被配置为当比较器的输出节点处的信号指示第一比较结果时，响应于温度相关的参考电流来增加比较器的第二输入节点处的电压电平，并且降低电压电平 当比较器的输出节点处的信号指示第二比较结果时，比较器的第二输入节点。

公开(公告)号：US20130106475A1

公开(公告)日：2013-05-02

申请号：US13718235

申请日：2012-12-18

Applicant: Chih-Chang LIN ,  Chan-Hong CHERN ,  Steven SWEI ,  Ming-Chieh HUANG ,  Tien-Chun YANG

Inventor： Chih-Chang LIN ,  Chan-Hong CHERN ,  Steven SWEI ,  Ming-Chieh HUANG ,  Tien-Chun YANG

IPC: H03L7/08

CPC classification number: H03L7/08 ,  H03L7/081 ,  H03L7/087

Abstract: A method of operating a charge pump of a phase-lock assistant circuit includes determining a first relative timing relationship of a phase of a data signal to a phase of a first phase clock. A second relative timing relationship of the phase of the data signal to a phase of a second phase clock is determined, and the first and second phase clocks have a 45° phase difference. An up signal and a down signal are generated in response to the first relative timing relationship and the second relative timing relationship. The charge pump circuit is driven according to the up signal and the down signal.

Abstract translation: 操作锁相辅助电路的电荷泵的方法包括确定数据信号的相位与第一相位时钟的相位的第一相对定时关系。 确定数据信号的相位与第二相位时钟的相位的第二相对定时关系，并且第一和第二相位时钟具有45°的相位差。 响应于第一相对定时关系和第二相对定时关系产生升高信号和下降信号。 电荷泵电路根据上升信号和下降信号进行驱动。