Method for eliminating contact bridge in contact hole process
    1.
    发明授权
    Method for eliminating contact bridge in contact hole process 有权
    消除接触孔过程中的接触桥的方法

    公开(公告)号:US09224589B2

    公开(公告)日:2015-12-29

    申请号:US13497768

    申请日:2011-11-28

    摘要: A method for eliminating contact bridge in a contact hole process is disclosed, wherein a cleaning menu comprising a multi-step adaptive protective thin film deposition process is provided, so that a stack adaptive protective thin film is formed on the sidewall of the chamber of the HDP CVD equipment. The stack adaptive protective thin film has good adhesivity, compactness and uniformity to protect the sidewall of the chamber of the HDP CVD equipment from being damaged by the plasma, and avoid the generation of defect particles, thereby improving the HDP CVD technical yield and eliminating the contact bridge phenomenon in the contact hole process.

    摘要翻译: 公开了一种用于消除接触孔工艺中的接触桥的方法,其中提供了包括多步自适应保护薄膜沉积工艺的清洁菜单,使得堆叠自适应保护薄膜形成在腔室的侧壁上 HDP CVD设备。 叠层自适应保护薄膜具有良好的粘合性,紧凑性和均匀性,以保护HDP CVD设备室的侧壁不被等离子体损坏,并避免产生缺陷颗粒,从而提高HDP CVD技术产量并消除 接触孔过程中的接触桥现象。

    Method of manufacturing semiconductor device
    3.
    发明授权
    Method of manufacturing semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号:US08853024B2

    公开(公告)日:2014-10-07

    申请号:US13812498

    申请日:2012-08-27

    IPC分类号: H01L21/8238

    摘要: The present invention discloses a method for manufacturing a semiconductor device comprising the steps of: forming a plurality of source and drain regions in a substrate; forming a plurality of gate spacer structures and an interlayer dielectric layer around the gate spacer structures on the substrate, wherein the gate spacer structures enclose a plurality of first gate trenches and a plurality of second gate trenches; sequentially depositing a first gate insulating layer and a second gate insulating layer, a first blocking layer and a second work function regulating layer in the first and second gate trenches; performing selective etching to remove the second work function regulating layer from the first gate trenches to expose the first blocking layer; depositing a first work function regulating layer on the first blocking layer in the first gate trenches and on the second work function regulating layer in the second gate trenches; and depositing a resistance regulating layer on the first work function regulating layer in the first gate trenches and on the first work function regulating layer in the second gate trench.

    摘要翻译: 本发明公开了一种制造半导体器件的方法,包括以下步骤:在衬底中形成多个源极和漏极区; 在所述衬底上的所述栅极隔离物结构周围形成多个栅极间隔物结构和层间电介质层,其中所述栅极间隔物结构包围多个第一栅极沟槽和多个第二栅极沟槽; 在第一和第二栅极沟槽中依次沉积第一栅极绝缘层和第二栅极绝缘层,第一阻挡层和第二功函数调节层; 执行选择性蚀刻以从第一栅极沟槽去除第二功函数调节层以暴露第一阻挡层; 在第一栅极沟槽中的第一阻挡层上和第二栅极沟槽中的第二功函数调节层上沉积第一功函数调节层; 以及在第一栅极沟槽中的第一功函数调节层和第二栅沟中的第一功函数调节层上沉积电阻调节层。

    MOS device for making the source/drain region closer to the channel region and method of manufacturing the same
    4.
    发明授权
    MOS device for making the source/drain region closer to the channel region and method of manufacturing the same 有权
    用于使源极/漏极区域更靠近沟道区域的MOS器件及其制造方法

    公开(公告)号:US08841190B2

    公开(公告)日:2014-09-23

    申请号:US13519884

    申请日:2012-04-10

    IPC分类号: H01L29/872

    摘要: This invention relates to a MOS device for making the source/drain region closer to the channel region and a method of manufacturing the same, comprising: providing an initial structure, which includes a substrate, an active region, and a gate stack; performing ion implantation in the active region on both sides of the gate stack, such that part of the substrate material undergoes pre-amorphization to form an amorphous material layer; forming a first spacer; with the first spacer as a mask, performing dry etching, thereby forming a recess, with the amorphous material layer below the first spacer kept; performing wet etching using an etchant solution that is isotropic to the amorphous material layer and whose etch rate to the amorphous material layer is greater than or substantially equal to the etch rate to the {100} and {110} surfaces of the substrate material but is far greater than the etch rate to the {111} surface of the substrate material, thus removing the amorphous material layer below the first spacer, such that the substrate material below the amorphous material layer is exposed to the solution and is etched thereby, and in the end, forming a Sigma shaped recess that extends to the nearby region below the gate stack; and epitaxially forming SiGe in the Sigma shaped recess.

    摘要翻译: 本发明涉及一种用于使源极/漏极区域更靠近沟道区域的MOS器件及其制造方法,包括:提供包括衬底,有源区域和栅极堆叠的初始结构; 在栅极堆叠的两侧上的有源区中进行离子注入,使得衬底材料的一部分经历预非晶化以形成无定形材料层; 形成第一间隔物; 以第一间隔物作为掩模,进行干蚀刻,从而形成凹部,保持第一间隔物下面的非晶材料层; 使用对非晶材料层各向同性的蚀刻剂溶液进行湿蚀刻,并且其对非晶材料层的蚀刻速率大于或基本上等于对基板材料的{100}和{110}表面的蚀刻速率,但是 远远大于衬底材料的{111}表面的蚀刻速率,从而去除第一间隔物下方的无定形材料层,使得无定形材料层下面的衬底材料暴露于溶液并被蚀刻,并且在 结束,形成延伸到栅堆叠下方的附近区域的Sigma形凹部; 并在Sigma形凹部中外延形成SiGe。

    Semiconductor device manufacturing method
    5.
    发明授权
    Semiconductor device manufacturing method 有权
    半导体器件制造方法

    公开(公告)号:US08716090B2

    公开(公告)日:2014-05-06

    申请号:US13580962

    申请日:2012-06-12

    IPC分类号: H01L21/336

    摘要: The present invention provides a manufacturing method for a semiconductor device having epitaxial source/drain regions, in which a diffusion barrier layer of the source/drain regions made of epitaxial silicon-carbon or germanium silicon-carbon are added on the basis of epitaxially growing germanium-silicon of the source/drain regions in the prior art process, and the introduction of the diffusion barrier layer of the source/drain regions prevents diffusion of the dopant in the source/drain regions, thus mitigating the SCE and DIBL effect. The use of the diffusion barrier layer for the source/drain regions can also reduce the dosage of HALO implantation in the subsequent step, thus if HALO is performed before epitaxial growth of the source/drain regions, impact on the surfaces of the source/drain regions can be alleviated; if HALO is performed after epitaxial growth of the source/drain regions, the stress release effect of the epitaxial layer of the source drain/regions caused by the implantation can be reduced as much as possible.

    摘要翻译: 本发明提供了一种具有外延源极/漏极区域的半导体器件的制造方法,其中基于外延生长锗添加由外延硅 - 碳或锗硅 - 碳制成的源极/漏极区的扩散阻挡层 在现有技术的工艺中源极/漏极区域的硅,以及源极/漏极区域的扩散阻挡层的引入防止了掺杂剂在源/漏区域中的扩散,从而减轻了SCE和DIBL效应。 用于源极/漏极区域的扩散阻挡层的使用也可以降低后续步骤中的HALO注入的剂量,因此如果在源极/漏极区域的外延生长之前执行HALO,则冲击源极/漏极 地区可以缓解; 如果在源/漏区的外延生长之后执行HALO,则可以尽可能地减少由注入引起的源漏极/区域的外延层的应力释放效应。

    Method for manufacturing a semiconductor device
    6.
    发明授权
    Method for manufacturing a semiconductor device 有权
    半导体器件的制造方法

    公开(公告)号:US08703567B2

    公开(公告)日:2014-04-22

    申请号:US13497744

    申请日:2011-11-29

    IPC分类号: H01L21/336

    摘要: The present invention discloses a method for manufacturing a semiconductor device, comprising: forming an insulating isolation layer on a substrate; forming an insulating isolation layer trench in the insulating isolation layer; forming an active region layer in the insulating isolation layer trench; forming a semiconductor device structure in and above the active region layer; characterized in that the carrier mobility of the active region layer is higher than that of the substrate. Said active region is formed of a material different from that of the substrate, the carrier mobility in the channel region is enhanced, thereby the device response speed is improved and the device performance is enhanced. Unlike the existing STI manufacturing process, for the present invention, an STI is formed first, and then filling is performed to form an active region, thus avoiding the problem of generation of holes in STI, and improving the device reliability.

    摘要翻译: 本发明公开了一种制造半导体器件的方法,包括:在衬底上形成绝缘隔离层; 在绝缘隔离层中形成绝缘隔离层沟槽; 在绝缘隔离层沟槽中形成有源区; 在有源区域层中形成半导体器件结构; 其特征在于,有源区层的载流子迁移率高于基板的载流子迁移率。 所述有源区由不同于衬底的材料形成,通道区域中的载流子迁移率增强,从而提高了器件响应速度并提高了器件性能。 与现有的STI制造方法不同,对于本发明,首先形成STI,然后进行填充以形成有源区,从而避免STI中产生孔的问题,并提高器件的可靠性。

    Semiconductor structure and method for manufacturing the same
    7.
    发明授权
    Semiconductor structure and method for manufacturing the same 有权
    半导体结构及其制造方法

    公开(公告)号:US09281398B2

    公开(公告)日:2016-03-08

    申请号:US14355664

    申请日:2012-07-03

    摘要: The present invention discloses a semiconductor device, which comprises a substrate, a gate stack structure on the substrate, a channel region in the substrate under the gate stack structure, and source and drain regions at both sides of the channel region, wherein there is a stressed layer under and at both sides of the channel region, in which the source and drain regions are formed. According to the semiconductor device and the method for manufacturing the same of the present invention, a stressed layer is formed at both sides of and under the channel region made of a silicon-based material so as to act on the channel region, thereby effectively increasing the carrier mobility of the channel region and improving the device performance.

    摘要翻译: 本发明公开了一种半导体器件,其包括衬底,衬底上的栅极堆叠结构,栅极堆叠结构下的衬底中的沟道区,以及沟道区两侧的源极和漏极区,其中存在 在形成源极和漏极区的沟道区的下侧和两侧具有应力层。 根据本发明的半导体器件及其制造方法,在由硅系材料制成的沟道区域的两侧和下方形成应力层,以作用于沟道区域,从而有效地增加 通道区域的载波移动性和设备性能的提高。

    Semiconductor structure and method for manufacturing the same
    8.
    发明授权
    Semiconductor structure and method for manufacturing the same 有权
    半导体结构及其制造方法

    公开(公告)号:US09082849B2

    公开(公告)日:2015-07-14

    申请号:US13580966

    申请日:2012-05-14

    摘要: The present invention provides a method for manufacturing a semiconductor structure, comprising the steps of: providing a semiconductor substrate, forming an insulating layer on the semiconductor substrate, and forming a semiconductor base layer on the insulating layer; forming a sacrificial layer and a spacer surrounding the sacrificial layer on the semiconductor base layer, and etching the semiconductor base layer by taking the spacer as a mask to form a semiconductor body; forming a dielectric film on sidewalls of the semiconductor body; removing the sacrificial layer and the semiconductor body located under the sacrificial layer to form a first semiconductor fin and a second semiconductor fin; and forming a retrograde doped well structure on the inner walls of the first semiconductor fin and the second semiconductor fin, wherein the inner walls thereof are opposite to each other. Correspondingly, the present invention further provides a semiconductor structure. In the present invention, a retrograde doped well structure is formed on the sidewalls of the two semiconductor fins that are opposite to each other, so that the width of the source/drain depletion layer may be effectively reduced, and thereby the short channel effect is reduced.

    摘要翻译: 本发明提供一种制造半导体结构的方法,包括以下步骤:提供半导体衬底,在半导体衬底上形成绝缘层,并在绝缘层上形成半导体基底层; 在所述半导体基底层上形成包围所述牺牲层的牺牲层和间隔物,并且通过以所述间隔物作为掩模来蚀刻所述半导体基底层以形成半导体本体; 在所述半导体主体的侧壁上形成电介质膜; 去除位于牺牲层下面的牺牲层和半导体本体以形成第一半导体鳍片和第二半导体鳍片; 以及在所述第一半导体翅片和所述第二半导体翅片的内壁上形成逆向掺杂的阱结构,其中所述内壁彼此相对。 相应地,本发明还提供一种半导体结构。 在本发明中,在两个相互相对的两个半导体鳍片的侧壁上形成逆向掺杂阱结构,从而可以有效地减小源/漏耗尽层的宽度,从而短沟道效应为 减少

    Semiconductor structure and method for manufacturing the same
    9.
    发明授权
    Semiconductor structure and method for manufacturing the same 有权
    半导体结构及其制造方法

    公开(公告)号:US08822334B2

    公开(公告)日:2014-09-02

    申请号:US13380612

    申请日:2011-04-18

    摘要: A method for manufacturing a semiconductor structure comprises: providing a substrate (100) on which a dummy gate stack is formed, forming a spacer (240) at sidewalls of the dummy gate stack, and forming a source/drain region (110) and a source/drain extension region (111) at both sides of the dummy gate stack; removing at least part of the spacer (240), to expose at least part of the source/drain extension region (111); forming a contact layer (112) on the source/drain region (110) and the exposed source/drain extension region (111), the contact layer (112) being [made of] one of CoSi2, NiSi and Ni(Pt)Si2-y or combinations thereof, and a thickness of the contact layer (112) being less than 10 nm. Correspondingly, the present invention further provides a semiconductor structure which is beneficial to reducing contact resistance and can maintain excellent performance in a subsequent high temperature process.

    摘要翻译: 一种用于制造半导体结构的方法,包括:提供其上形成有虚拟栅极堆叠的衬底(100),在所述虚拟栅极堆叠的侧壁处形成间隔物(240),以及形成源/漏区(110)和 源极/漏极延伸区域(111); 去除所述间隔物(240)的至少一部分,以暴露所述源极/漏极延伸区域(111)的至少一部分; 在源/漏区(110)和暴露的源极/漏极延伸区(111)上形成接触层(112),接触层(112)由CoSi2,NiSi和Ni(Pt)Si2 -y或其组合,并且接触层(112)的厚度小于10nm。 相应地,本发明还提供一种半导体结构,该半导体结构有利于降低接触电阻并且可以在随后的高温工艺中保持优异的性能。

    Semiconductor structure and method for manufacturing the same
    10.
    发明授权
    Semiconductor structure and method for manufacturing the same 有权
    半导体结构及其制造方法

    公开(公告)号:US08809134B2

    公开(公告)日:2014-08-19

    申请号:US13640735

    申请日:2012-05-17

    申请人: Haizhou Yin Wei Jiang

    发明人: Haizhou Yin Wei Jiang

    摘要: A method of manufacturing a semiconductor structure, which comprises the steps of: providing a substrate, forming a fin on the substrate, which comprises a central portion for forming a channel and an end portion for forming a source/drain region and a source/drain extension region; forming a gate stack to cover the central portion of the fin; performing light doping to form a source/drain extension region in the end portion of the fin; forming a spacer on sidewalls of the gate stack; performing heavy doping to form a source/drain region in the end portion of the fin; removing at least a part of the spacer to expose at least a part of the source/drain extension region; forming a contact layer on an upper surface of the source/drain region and an exposed area of the source/drain extension region. Correspondingly, the present invention also provides a semiconductor structure. By forming a thin contact layer in the source/drain extension region, the present invention can not only effectively reduce the contact resistance of the source/drain extension region, but also effectively control the junction depth of the source/drain extension region by controlling the thickness of the contact layer, thereby suppressing the short channel effect.

    摘要翻译: 一种制造半导体结构的方法,包括以下步骤:提供衬底,在衬底上形成翅片,其包括用于形成沟道的中心部分和用于形成源极/漏极区域的端部和源极/漏极 延伸区域 形成栅极堆叠以覆盖鳍片的中心部分; 执行轻掺杂以在鳍的端部形成源/漏延伸区; 在所述栅极堆叠的侧壁上形成间隔物; 进行重掺杂以在鳍的端部形成源/漏区; 去除所述间隔物的至少一部分以暴露所述源极/漏极延伸区域的至少一部分; 在源极/漏极区域的上表面和源极/漏极延伸区域的暴露区域上形成接触层。 相应地,本发明还提供一种半导体结构。 通过在源极/漏极延伸区域中形成薄的接触层,本发明不仅可以有效地降低源极/漏极延伸区域的接触电阻,而且可以通过控制源极/漏极延伸区域的结深度来有效地控制源极/漏极延伸区域的结深度 接触层的厚度,从而抑制短沟道效应。