公开(公告)号：US20120205728A1

公开(公告)日：2012-08-16

申请号：US13379658

申请日：2011-02-27

Applicant: Haizhou Yin ,  Jun Luo ,  Huilong Zhu ,  Zhijiong Luo

Inventor： Haizhou Yin ,  Jun Luo ,  Huilong Zhu ,  Zhijiong Luo

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/28518 ,  H01L21/28185 ,  H01L21/76814 ,  H01L29/49 ,  H01L29/517 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/7833

Abstract: The present invention provides a method for manufacturing a semiconductor structure, comprising: providing a substrate, and forming a dummy gate stack on the substrate, sidewall spacers on sidewalls of the dummy gate stack, and source/drain regions at both sides of the dummy gate stack, wherein the dummy gate stack comprising a dummy gate; forming a first contact layer on surfaces of the source/drain regions; forming an interlayer dielectric layer to cover the first contact layer; removing the dummy gate or the dummy gate stack material to form an opening, filling the opening with a first conductive material or with a gate dielectric layer and a first conductive material to form a gate stack structure; forming through holes within the interlayer dielectric layer, so that a portion of the first contact layer or a portion of the first contact layer and the source/drain regions are exposed in the through holes; forming a second contact layer on the exposed portions of the regions; filling the through holes with a second conductive material to form contact vias. Besides, the present invention further provides a semiconductor structure, which is favorable for reducing the contact resistance.

Abstract translation: 本发明提供一种制造半导体结构的方法，包括：提供衬底，在衬底上形成虚设栅极叠层，在虚拟栅极堆叠的侧壁上形成侧壁间隔物，以及虚拟栅极两侧的源极/漏极区域 堆叠，其中所述伪栅极堆叠包括虚拟栅极; 在所述源/漏区的表面上形成第一接触层; 形成层间电介质层以覆盖所述第一接触层; 去除伪栅极或虚拟栅极堆叠材料以形成开口，用第一导电材料或栅极电介质层和第一导电材料填充开口以形成栅极堆叠结构; 在所述层间电介质层内形成通孔，使得所述第一接触层的一部分或所述第一接触层的一部分和所述源/漏区在所述通孔中露出; 在所述区域的所述暴露部分上形成第二接触层; 用第二导电材料填充通孔以形成接触孔。 此外，本发明还提供了有利于降低接触电阻的半导体结构。

公开(公告)号：US08835316B2

公开(公告)日：2014-09-16

申请号：US13378997

申请日：2011-08-09

Applicant: Haizhou Yin ,  Jun Luo ,  Huilong Zhu ,  Zhijiong Luo

Inventor： Haizhou Yin ,  Jun Luo ,  Huilong Zhu ,  Zhijiong Luo

IPC: H01L29/772 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/285

CPC classification number: H01L29/7833 ,  H01L21/28518 ,  H01L21/32139 ,  H01L21/76897 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/6659

Abstract: The disclosure provides a transistor, a method for manufacturing the transistor, and a semiconductor chip comprising the transistor. The transistor comprises: an active area, a gate stack, a primary spacer, and source/drain regions, wherein the active area is on a semiconductor substrate; the gate stack, the primary spacer, and the source/drain regions are on the active area; the primary spacer surrounds the gate stack; the source/drain regions are embedded in the active area and self-aligned with opposite sides of the primary spacer. Wherein the transistor further comprises: a silicide spacer, wherein the silicide spacer is located at opposite sides of the primary spacer, and a dielectric material is filled between the two ends of the silicide spacer in the width direction of the gate stack, so as to isolate the source/drain regions from each other.

Abstract translation: 本发明提供一种晶体管，一种晶体管的制造方法和一种包括该晶体管的半导体芯片。 晶体管包括：有源区，栅极堆叠，初级间隔物和源/漏区，其中有源区在半导体衬底上; 栅极堆叠，初级间隔物和源极/漏极区域在有源区域上; 主要间隔物围绕栅极堆叠; 源极/漏极区域被嵌入有源区域中并且与主隔板的相对侧自对准。 其中，所述晶体管还包括：硅化物间隔物，其中所述硅化物间隔物位于所述主间隔物的相对侧，并且电介质材料填充在所述硅化物间隔物的所述栅堆叠的宽度方向的两端之间，以便 将源极/漏极区彼此隔离。

公开(公告)号：US20130009217A1

公开(公告)日：2013-01-10

申请号：US13378997

申请日：2011-08-09

Applicant: Haizhou Yin ,  Jun Luo ,  Huilong Zhu ,  Zhijiong Luo

Inventor： Haizhou Yin ,  Jun Luo ,  Huilong Zhu ,  Zhijiong Luo

IPC: H01L29/772 ,  H01L21/336

CPC classification number: H01L29/7833 ,  H01L21/28518 ,  H01L21/32139 ,  H01L21/76897 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/6659

Abstract: It is provided a transistor, a method for manufacturing the transistor, and a semiconductor chip comprising the transistor. A method for manufacturing a transistor may comprise: defining an active area on a semiconductor substrate, and forming on the active area a gate stack, a primary spacer, and source/drain regions, wherein the primary spacer surrounds the gate stack, and the source/drain regions are embedded in the active area and self-aligned with opposite sides of the primary spacer; forming a semiconductor spacer surrounding the primary spacer, and cutting off the ends of the semiconductor spacer in the width direction of the gate stack so as to isolate the source/drain regions from each other; and covering the surfaces of the source/drain regions and the semiconductor spacer with a layer of metal or alloy, and annealing the resulting structure, so that a metal silicide is formed on the surfaces of the source/drain regions, and so that the semiconductor spacer is transformed into a silicide spacer simultaneously. As such, the risk of transistor failure due to atoms or ions of Ni entering the channel region through the source/drain extension regions is reduced.

Abstract translation: 提供晶体管，晶体管的制造方法和包括晶体管的半导体芯片。 一种用于制造晶体管的方法可以包括：在半导体衬底上限定有源区，以及在有源区上形成栅极堆叠，初级间隔物和源极/漏极区，其中主要间隔物包围栅极堆叠，源极 /漏极区域嵌入有源区域并与主间隔物的相对侧自对准; 形成围绕所述初级间隔物的半导体衬垫，并且在所述栅极叠层的宽度方向上切断所述半导体衬垫的端部，以将所述源极/漏极区彼此隔离; 并且用金属或合金层覆盖源极/漏极区域和半导体衬垫的表面，并对所得结构进行退火，使得在源极/漏极区域的表面上形成金属硅化物，并且使得半导体 间隔物同时转化成硅化物间隔物。 因此，由于通过源极/漏极延伸区域进入沟道区域的Ni的原子或离子导致的晶体管故障的风险降低。

公开(公告)号：US08822334B2

公开(公告)日：2014-09-02

申请号：US13380612

申请日：2011-04-18

Applicant: Haizhou Yin ,  Jun Luo ,  Zhijiong Luo ,  Huilong Zhu

Inventor： Haizhou Yin ,  Jun Luo ,  Zhijiong Luo ,  Huilong Zhu

IPC: H01L21/44 ,  H01L29/45 ,  H01L21/285 ,  H01L29/66

CPC classification number: H01L29/6653 ,  H01L21/28518 ,  H01L29/456 ,  H01L29/66545

Abstract: A method for manufacturing a semiconductor structure comprises: providing a substrate (100) on which a dummy gate stack is formed, forming a spacer (240) at sidewalls of the dummy gate stack, and forming a source/drain region (110) and a source/drain extension region (111) at both sides of the dummy gate stack; removing at least part of the spacer (240), to expose at least part of the source/drain extension region (111); forming a contact layer (112) on the source/drain region (110) and the exposed source/drain extension region (111), the contact layer (112) being [made of] one of CoSi2, NiSi and Ni(Pt)Si2-y or combinations thereof, and a thickness of the contact layer (112) being less than 10 nm. Correspondingly, the present invention further provides a semiconductor structure which is beneficial to reducing contact resistance and can maintain excellent performance in a subsequent high temperature process.

Abstract translation: 一种用于制造半导体结构的方法，包括：提供其上形成有虚拟栅极堆叠的衬底（100），在所述虚拟栅极堆叠的侧壁处形成间隔物（240），以及形成源/漏区（110）和 源极/漏极延伸区域（111）; 去除所述间隔物（240）的至少一部分，以暴露所述源极/漏极延伸区域（111）的至少一部分; 在源/漏区（110）和暴露的源极/漏极延伸区（111）上形成接触层（112），接触层（112）由CoSi2，NiSi和Ni（Pt）Si2 -y或其组合，并且接触层（112）的厚度小于10nm。 相应地，本发明还提供一种半导体结构，该半导体结构有利于降低接触电阻并且可以在随后的高温工艺中保持优异的性能。

公开(公告)号：US08642471B2

公开(公告)日：2014-02-04

申请号：US13379658

申请日：2011-02-27

Applicant: Haizhou Yin ,  Jun Luo ,  Huilong Zhu ,  Zhijiong Luo

Inventor： Haizhou Yin ,  Jun Luo ,  Huilong Zhu ,  Zhijiong Luo

IPC: H01L29/78 ,  H01L29/94

CPC classification number: H01L21/28518 ,  H01L21/28185 ,  H01L21/76814 ,  H01L29/49 ,  H01L29/517 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/7833

Abstract: The present invention provides a method for manufacturing a semiconductor structure. The method can effectively reduce the contact resistance between source/drain regions and a contact layer by forming two contact layers of different thickness on the surfaces of the source/drain regions. Further, the present invention provides a semiconductor structure, which has reduced the contact resistance.

Abstract translation: 本发明提供一种半导体结构的制造方法。 该方法可以通过在源极/漏极区域的表面上形成不同厚度的两个接触层来有效地降低源极/漏极区域和接触层之间的接触电阻。 此外，本发明提供一种降低了接触电阻的半导体结构。

公开(公告)号：US20120217589A1

公开(公告)日：2012-08-30

申请号：US13380612

申请日：2011-04-18

Applicant: Haizhou Yin ,  Jun Luo ,  Zhijiong Luo ,  Huilong Zhu

Inventor： Haizhou Yin ,  Jun Luo ,  Zhijiong Luo ,  Huilong Zhu

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/6653 ,  H01L21/28518 ,  H01L29/456 ,  H01L29/66545

Abstract: A method for manufacturing a semiconductor structure comprises: providing a substrate (100) on which a dummy gate stack is formed, forming a spacer (240) at sidewalls of the dummy gate stack, and forming a source/drain region (110) and a source/drain extension region (111) at both sides of the dummy gate stack; removing at least part of the spacer (240), to expose at least part of the source/drain extension region (111); forming a contact layer (112) on the source/drain region (110) and the exposed source/drain extension region (111), the contact layer (112) being [made of] one of CoSi2, NiSi and Ni(Pt)Si2-y or combinations thereof, and a thickness of the contact layer (112) being less than 10 nm. Correspondingly, the present invention further provides a semiconductor structure which is beneficial to reducing contact resistance and can maintain excellent performance in a subsequent high temperature process.

Abstract translation: 一种用于制造半导体结构的方法，包括：提供其上形成有虚拟栅极堆叠的衬底（100），在所述虚拟栅极堆叠的侧壁处形成间隔物（240），以及形成源/漏区（110）和 源极/漏极延伸区域（111）; 去除所述间隔物（240）的至少一部分，以暴露所述源极/漏极延伸区域（111）的至少一部分; 在源/漏区（110）和暴露的源极/漏极延伸区（111）上形成接触层（112），接触层（112）由CoSi2，NiSi和Ni（Pt）Si2 -y或其组合，并且接触层（112）的厚度小于10nm。 相应地，本发明还提供一种半导体结构，该半导体结构有利于降低接触电阻并且可以在随后的高温工艺中保持优异的性能。

公开(公告)号：US09356025B2

公开(公告)日：2016-05-31

申请号：US14348579

申请日：2012-03-29

Applicant: Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin

Inventor： Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin

IPC: H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/66575 ,  H01L29/7846

Abstract: The present invention relates to enhancing MOSFET performance with the corner stresses of STI. A method of manufacturing a MOS device comprises the steps of: providing a semiconductor substrate; forming trenches on the semiconductor substrate and at least a pMOS region and at least an nMOS region surrounded by the trenches; filling the trenches with a dielectric material having a stress; removing at least the dielectric material having a stress in the trenches which is adjacent to a position where a channel is to be formed on each of the pMOS and nMOS regions so as to form exposed regions; filling the exposed regions with a insulating material; and forming pMOS and nMOS devices on the pMOS region and the nMOS region, respectively, wherein each of the pMOS and nMOS devices comprises a channel, a gate formed above the channel, and a source and a drain formed at both sides of the channel; wherein in a channel length direction, the boundary of each exposed region is substantially aligned with the boundary of the position of the channel, or the boundary of each exposed region extends along the channel length direction to be aligned with the boundary of corresponding pMOS or nMOS region.

Abstract translation: 本发明涉及利用STI的拐角应力来增强MOSFET的性能。 一种制造MOS器件的方法包括以下步骤：提供半导体衬底; 在所述半导体衬底和至少一个pMOS区域和由所述沟槽包围的至少nMOS区域中形成沟槽; 用具有应力的介电材料填充沟槽; 至少去除在沟道中具有应力的介电材料，所述沟槽邻近要在pMOS和nMOS区域中的每一个上形成沟道的位置，以形成暴露区域; 用绝缘材料填充暴露的区域; 以及分别在pMOS区域和nMOS区域上形成pMOS和nMOS器件，其中pMOS和nMOS器件中的每一个包括沟道，形成在沟道上方的栅极以及形成在沟道两侧的源极和漏极; 其中在通道长度方向上，每个曝光区域的边界基本上与通道位置的边界对齐，或者每个曝光​​区域的边界沿着沟道长度方向延伸以与对应的pMOS或nMOS的边界对准 地区。

公开(公告)号：US09054221B2

公开(公告)日：2015-06-09

申请号：US13510807

申请日：2011-11-18

Applicant: Huilong Zhu ,  Qingqing Liang ,  Zhijiong Luo ,  Haizhou Yin

Inventor： Huilong Zhu ,  Qingqing Liang ,  Zhijiong Luo ,  Haizhou Yin

IPC: H01L27/088 ,  H01L21/336 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L21/84 ,  H01L27/1203

Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: an SOI wafer comprising a semiconductor substrate, a buried insulation layer, and a semiconductor layer, wherein the buried insulation layer is disposed on the semiconductor substrate, and the semiconductor layer is disposed on the buried insulation layer; a plurality of MOSFETs being formed adjacently to each other in the SOI wafer, wherein each of the MOSFETs comprises a respective backgate being formed in the semiconductor substrate; and a plurality of shallow trench isolations, each of which being formed between respective adjacent MOSFETs to isolate the respective adjacent MOSFETs from each other, wherein the respective adjacent MOSFETs share a common backgate isolation region under and in direct contact with the respective backgate in the semiconductor substrate, and a PNP junction or an NPN junction is formed by the common backgate isolation region and the respective backgate of the respective adjacent MOSFETs. According to the present disclosure, respective backgates of two adjacent MOSFETs are isolated from each other by the shallow trench isolation. Furthermore, the two adjacent MOSFETs are also isolated from each other by the PNP or NPN junction formed by the respective backgates of the two adjacent MOSFETs and the common backgate isolation. As a result, this device structure has a better insulation effect over the prior art MOSFET and it greatly reduces the possibility of breakthrough.

Abstract translation: 本发明提供一种半导体器件及其制造方法。 半导体器件包括：SOI晶片，其包括半导体衬底，掩埋绝缘层和半导体层，其中所述掩埋绝缘层设置在所述半导体衬底上，并且所述半导体层设置在所述掩埋绝缘层上; 在SOI晶片中彼此相邻形成的多个MOSFET，其中每个MOSFET包括形成在半导体衬底中的相应后栅; 以及多个浅沟槽隔离，其中每一个均形成在各个相邻的MOSFET之间，以将各个相邻的MOSFET彼此隔离，其中相应的相邻MOSFET在半导体内部和相应的后栅极直接接触并与之直接接触。 衬底，并且PNP结或NPN结由公共背栅隔离区和相应的相邻MOSFET的相应背栅形成。 根据本公开，两个相邻MOSFET的相应背板通过浅沟槽隔离彼此隔离。 此外，两个相邻的MOSFET也通过由两个相邻MOSFET的相应后沿和公共背栅隔离形成的PNP或NPN结彼此隔离。 结果，该器件结构具有比现有技术的MOSFET更好的绝缘效果，并且大大降低了突破的可能性。

公开(公告)号：US08981454B2

公开(公告)日：2015-03-17

申请号：US13061461

申请日：2010-09-25

Applicant: Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo

Inventor： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo

IPC: H01L29/788 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L21/845 ,  H01L29/42324 ,  H01L29/785 ,  H01L29/7881

Abstract: The present application discloses a non-volatile memory device, comprising a semiconductor fin on an insulating layer; a channel region at a central portion of the semiconductor fin; source/drain regions on both sides of the semiconductor fin; a floating gate arranged at a first side of the semiconductor fin and extending in a direction further away from the semiconductor fin; and a first control gate arranged on top of the floating gate or covering top and sidewall portions of the floating gate. The non-volatile memory device reduces a short channel effect, has an increased memory density, and is cost effective.

Abstract translation: 本申请公开了一种非易失性存储器件，其包括绝缘层上的半导体鳍片; 在半导体鳍片的中心部分处的沟道区域; 半导体鳍片两侧的源极/漏极区域; 布置在半导体鳍片的第一侧并沿远离半导体鳍片的方向延伸的浮动栅极; 以及布置在所述浮动栅极的顶部上或覆盖所述浮动栅极的顶部和侧壁部分的第一控制栅极。 非易失性存储器件减少短通道效应，具有增加的存储器密度，并且是成本有效的。

公开(公告)号：US08952453B2

公开(公告)日：2015-02-10

申请号：US13580053

申请日：2011-11-18

Applicant: Huilong Zhu ,  Qingqing Liang ,  Haizhou Yin ,  Zhijiong Luo

Inventor： Huilong Zhu ,  Qingqing Liang ,  Haizhou Yin ,  Zhijiong Luo

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L29/66545 ,  H01L29/78648

Abstract: The present application discloses a MOSFET and a method for manufacturing the same. The MOSFET is formed on an SOI wafer, comprising: a shallow trench isolation for defining an active region in the semiconductor layer; a gate stack on the semiconductor layer; a source region and a drain region in the semiconductor layer on both sides of the gate stack; a channel region in the semiconductor layer and sandwiched by the source region and the drain region; a back gate in the semiconductor substrate; a first dummy gate stack overlapping with a boundary between the semiconductor layer and the shallow trench isolation; and a second dummy gate stack on the shallow trench isolation, wherein the MOSFET further comprises a plurality of conductive vias which are disposed between the gate stack and the first dummy gate stack and electrically connected to the source region and the drain region respectively, and between the first dummy gate stack and the second dummy gate stack and electrically connected to the back gate. The MOSFET avoids short circuit between the back gate and the source/drain regions by the dummy gate stacks.

Abstract translation: 本申请公开了一种MOSFET及其制造方法。 MOSFET形成在SOI晶片上，包括：用于限定半导体层中的有源区的浅沟槽隔离; 半导体层上的栅极堆叠; 栅极堆叠的两侧的半导体层中的源极区域和漏极区域; 半导体层中的沟道区，被源极区和漏极区夹持; 半导体衬底中的背栅; 与半导体层和浅沟槽隔离之间的边界重叠的第一虚拟栅极堆叠; 以及在浅沟槽隔离上的第二虚拟栅极堆叠，其中所述MOSFET还包括多个导电通孔，所述多个导电通孔设置在所述栅极堆叠和所述第一伪栅极堆叠之间，并分别电连接到所述源极区域和所述漏极区域之间，以及 第一虚拟栅极堆叠和第二虚拟栅极堆叠并且电连接到背栅极。 MOSFET通过虚拟栅极堆叠避免了背栅极和源极/漏极区域之间的短路。