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公开(公告)号：US09906208B2
公开(公告)日：2018-02-27
申请号：US15462702
申请日：2017-03-17
发明人： Matt Allison , Eric S. Shapiro
摘要： An electronic system that includes a digitally selectable phase shifter circuit and an insertion loss fine adjustment circuit such that the system as a whole exhibits little or no change in insertion loss when changing phase state, and/or a digitally selectable attenuator circuit and a phase fine adjustment circuit such that the system as a whole exhibits little or no effect on phase when changing attenuation state. Included are methods for selecting adjustment control words for such circuits.
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公开(公告)号：US09887695B2
公开(公告)日：2018-02-06
申请号：US14987360
申请日：2016-01-04
IPC分类号： H01L29/49 , H03K17/16 , H03K17/10 , H03K17/284 , H03K17/687 , H03K17/689 , H03K17/04 , H03K17/06 , H03K17/08
CPC分类号： H03K17/161 , H03K17/04 , H03K17/06 , H03K17/08 , H03K17/102 , H03K17/284 , H03K17/6874 , H03K17/689 , H03K2217/0009
摘要： A circuit and method for controlling charge injection in a circuit are disclosed. In one embodiment, the circuit and method are employed in a semiconductor-on-insulator (SOI) Radio Frequency (RF) switch. In one embodiment, an SOI RF switch comprises a plurality of switching transistors coupled in series, referred to as “stacked” transistors, and implemented as a monolithic integrated circuit on an SOI substrate. Charge injection control elements are coupled to receive injected charge from resistively-isolated nodes located between the switching transistors, and to convey the injected charge to at least one node that is not resistively-isolated. In one embodiment, the charge injection control elements comprise resistors. In another embodiment, the charge injection control elements comprise transistors. A method for controlling charge injection in a switch circuit is disclosed whereby injected charge is generated at resistively-isolated nodes between series coupled switching transistors, and the injected charge is conveyed to at least one node of the switch circuit that is not resistively-isolated.
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公开(公告)号：US09866212B2
公开(公告)日：2018-01-09
申请号：US15061909
申请日：2016-03-04
IPC分类号： H01L21/00 , H03K17/687 , H03K17/10 , H03K17/16 , H03K17/693 , H01H11/00 , H03K17/06
CPC分类号： H03K17/6871 , H01H11/00 , H03K17/102 , H03K17/161 , H03K17/693 , H03K2017/066 , Y10T29/49105
摘要： An RF switch to controllably withstand an applied RF voltage Vsw, or a method of fabricating such a switch, which includes a string of series-connected constituent FETs with a node of the string between each pair of adjacent FETs. The method includes controlling capacitances between different nodes of the string to effectively tune the string capacitively, which will reduce the variance in the RF switch voltage distributed across each constituent FET, thereby enhancing switch breakdown voltage. Capacitances are controlled, for example, by disposing capacitive features between nodes of the string, and/or by varying design parameters of different constituent FETs. For each node, a sum of products of each significant capacitor by a proportion of Vsw appearing across it may be controlled to approximately zero.
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公开(公告)号：US09847715B2
公开(公告)日：2017-12-19
申请号：US15272935
申请日：2016-09-22
摘要： A power-conversion apparatus includes active-semiconductor switches configured to transition between first and second states that result in corresponding first and second electrical interconnections between capacitors and at least one of first and second terminals configured to be coupled to first and second external circuits at corresponding first and second voltages, a pre-charge circuit coupled to at least one of the capacitors, and gate-driver circuits, each of which includes a control input, power connections, and a drive output. Each switch is coupled to and controlled by a drive output of one of the gate-driver circuits. Power for the gate-driver circuits comes from charge stored on at least one of the capacitors via the power connection of that gate-driver circuit.
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公开(公告)号：US09847712B2
公开(公告)日：2017-12-19
申请号：US14776939
申请日：2013-12-30
CPC分类号： H02M3/07 , H02M1/32 , H02M3/073 , H02M2003/075
摘要： Transient or fault conditions for a switched capacitor power converter are detected by measuring one or more of internal voltages and/or currents associated with switching elements (e.g., transistors) or phase nodes, or voltages or currents at terminals of the converter, and based on these measurements detect that a condition has occurred when the measurements deviate from a predetermined range. Upon detection of the condition fault control circuitry alters operation of the converter, for example, by using a high voltage switch to electrically disconnect at least some of the switching elements from one or more terminals of the converter, or by altering timing characteristics of the phase signals.
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公开(公告)号：US09837325B2
公开(公告)日：2017-12-05
申请号：US14741303
申请日：2015-06-16
发明人： Mark Moffat , Andrew Christie , Duncan Pilgrim
CPC分类号： H01L22/14 , H01L22/32 , H01L23/15 , H01L23/3121 , H01L23/66 , H01L24/13 , H01L24/16 , H01L24/48 , H01L24/97 , H01L2223/6627 , H01L2224/131 , H01L2224/16227 , H01L2224/16235 , H01L2224/48227 , H01L2224/94 , H01L2224/97 , H01L2924/00014 , H01L2924/10253 , H01L2924/14 , H01L2924/1421 , H01L2924/15159 , H01L2924/15162 , H01L2924/15192 , H01L2924/15787 , H01L2924/16251 , H01L2224/11 , H01L2224/81 , H01L2924/014 , H01L2224/85 , H01L2224/45099
摘要： An extension of conventional IC fabrication processes to include some of the concepts of flip-chip assemblies while producing a final “non-flip chip” circuit structure suitable for conventional packaging or for direct usage by customers. Multiple IC dies are fabricated on a semiconductor wafer in a conventional fashion, solder bumped, and singulated. The singulated dies are then flip-chip assembled onto a single tile substrate of thin-film material which has been patterned with vias, peripheral connection pads, and one or more ground planes. Once dies are flip-chip mounted to the thin-film tile, all of the dies on the entire tile may be probed using automated testing equipment. Once test probing is complete, the dies and tile are singulated into die/tile assemblies.
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公开(公告)号：US09780728B1
公开(公告)日：2017-10-03
申请号：US15083939
申请日：2016-03-29
发明人： Daoud Salameh
IPC分类号： H03D7/02 , H03D7/14 , H03H7/42 , H01L23/66 , H01L27/06 , H01L27/12 , H01L27/092 , H01L29/78 , H01L29/786 , H01L21/84 , H01L21/86 , H01L21/8238
CPC分类号： H03D7/1458 , H01L21/8238 , H01L21/84 , H01L21/86 , H01L23/66 , H01L27/0629 , H01L27/092 , H01L27/1203 , H01L29/7838 , H01L29/786 , H03D7/02 , H03D7/1408 , H03D7/1441
摘要： A FET based double balanced mixer (DBM) that exhibits good conversion gain and IIP3 values and provides improved linearity and wide bandwidth. In one embodiment, a first balun is configured to receive a local oscillator (LO) signal and generate two balanced LO signals that are coupled to two corresponding opposing nodes of a four-node FET ring. A second balun is configured to pass an RF signal on the unbalanced side. The FET ring includes at least four FETs connected as branches of a ring, with the source of each FET connected to the drain of a next FET in the ring. Each FET is preferably fabricated as, or configured as, a low threshold voltage device having its gate connected to its drain, which causes the FET to operate as a diode, but with the unique characteristic of having close to a zero turn-on voltage.
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公开(公告)号：US09729107B2
公开(公告)日：2017-08-08
申请号：US14821501
申请日：2015-08-07
IPC分类号： H03F3/04 , H03G3/00 , H03F1/02 , H03F3/193 , H03F3/21 , H03F1/22 , H03F1/32 , H03F1/56 , H03F3/195 , H03F3/24 , H03F3/45 , H03F3/191
CPC分类号： H03F1/0205 , H03F1/0216 , H03F1/0222 , H03F1/0227 , H03F1/0244 , H03F1/025 , H03F1/0277 , H03F1/223 , H03F1/3247 , H03F1/3282 , H03F1/56 , H03F3/191 , H03F3/193 , H03F3/195 , H03F3/21 , H03F3/211 , H03F3/24 , H03F3/45179 , H03F3/45183 , H03F3/45188 , H03F2200/102 , H03F2200/108 , H03F2200/129 , H03F2200/15 , H03F2200/18 , H03F2200/213 , H03F2200/222 , H03F2200/336 , H03F2200/387 , H03F2200/408 , H03F2200/411 , H03F2200/451 , H03F2200/534 , H03F2200/537 , H03F2200/541 , H03F2200/546 , H03F2200/78 , H03F2201/3233 , H03F2203/45112 , H03F2203/45366 , H03F2203/45544 , H03F2203/45638 , H03F2203/45731
摘要： Various envelope tracking amplifiers are presented that can be switched between an ET (envelope tracking) mode and a non-ET mode. Switches and/or tunable components are utilized in constructing the envelope tracking amplifiers that can be switched between the ET mode and the non-ET mode.
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公开(公告)号：US09716475B1
公开(公告)日：2017-07-25
申请号：US15003463
申请日：2016-01-21
发明人： Hossein Noori
CPC分类号： H03F1/42 , H03F1/223 , H03F3/195 , H03F3/211 , H03F3/72 , H03F2200/111 , H03F2200/231 , H03F2200/294 , H03F2200/451 , H03F2200/72 , H03F2200/75 , H03F2203/21109 , H03F2203/21112 , H03F2203/7209
摘要： A selectable low noise amplifier (LNA) system comprising, a plurality of LNAs having a plurality of LNA characteristics and at least one selection switch network coupled to the plurality of LNAs to select at least one of the plurality of LNAs.
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公开(公告)号：US09712120B2
公开(公告)日：2017-07-18
申请号：US14794699
申请日：2015-07-08
发明人： Dan William Nobbe , David Halchin
CPC分类号： H03F1/3223 , H03F1/0205 , H03F1/30 , H03F3/193 , H03F3/195 , H03F3/72 , H03F2200/105 , H03F2200/324 , H03F2200/387 , H03F2200/451 , H03F2200/468 , H03G3/3036
摘要： Methods and systems for optimizing amplifier operations are described. The described methods and systems particularly describe a feed-forward control circuit that may also be used as a feed-back control circuit in certain applications. The feed-forward control circuit provides a control signal that may be used to configure an amplifier in a variety of ways.
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