公开(公告)号：US20250015775A1

公开(公告)日：2025-01-09

申请号：US18770370

申请日：2024-07-11

Applicant: pSemi Corporation

Inventor： Vikas Sharma ,  Peter Bacon

IPC: H03H7/25 ,  H03H7/20 ,  H03H11/20 ,  H03H11/24 ,  H03K17/687

Abstract: Digital step attenuator (DSA) and digital phase shifter (DPS) multi-stage circuit architectures that provide for high resolution. Embodiments use a dithering approach to weight bit positions to provide a much finer resolution than the lowest-valued individual stage. Bit position weights for stages are determined so as to enable selection of combinations of n bit positions that provide a desired total attenuation or phase shift range while allowing utilization of the large number of states (2n) available to produce fractional intermediate steps of attenuation or phase shift. The fractional intermediate steps have a resolution finer than the lowest-valued stage. Bit position weights may be determined using a weighting function, including weightings determined from a linear series, a geometric series, a harmonic series, or alternating variants of such series. In some embodiments, at least one bit position has a fixed value that is not determined by the bit position weighting function.

公开(公告)号：US20240405741A1

公开(公告)日：2024-12-05

申请号：US18205519

申请日：2023-06-03

Applicant: Anton Manolescu

Inventor： Anton Manolescu

IPC: H03H7/24 ,  H03H11/24

Abstract: An attenuator is described, obtained from a single resistive film deposited on an insulated substrate provided with three or more conductive terminals serving as input, output and common electrodes for electrical signals. These terminals are formed over the edges of the resistive film in a proper manner so as their position, lengths and the shape of the resistive film determine an uniform electric field and uniform current density lines throughout the resistive film with a precise ratio between the input current and the output current, and specific input and output resistances. The reliability of the attenuator is significantly improved.

公开(公告)号：US12063020B2

公开(公告)日：2024-08-13

申请号：US17989732

申请日：2022-11-18

Applicant: MACOM Technology Solutions Holdings, Inc.

Inventor： Jean-Marc Mourant

IPC: H03K17/00 ,  H03H11/24 ,  H03K5/01 ,  H03K17/16 ,  H03K17/687 ,  H03K17/693

CPC classification number: H03H11/245 ,  H03K5/01 ,  H03K17/164 ,  H03K17/687 ,  H03K17/6874 ,  H03K17/693

Abstract: A digital step attenuator (DSA) cell and related method are provided. The DSA cell includes a first branch comprising a first resistor connected, at a first side, to an input port and, at a second side, to an output port; a second resistor connected, at a first side, to the first resistor and, at a second side, to a first transistor and a third resistor connected, at a first side, to the first resistor and, at a second side, to a second transistor. Also included in the DSA cell is a second branch, in a parallel configuration with the first resistor, that includes a fourth resistor and a third transistor. Also included is a third branch, in a parallel configuration with the first resistor, that includes a fourth transistor. The first transistor, the second transistor, the third transistor, and the fourth transistor are configured to be operated independently.

公开(公告)号：US20240243732A1

公开(公告)日：2024-07-18

申请号：US18395930

申请日：2023-12-26

Applicant: MEDIATEK INC.

Inventor： Wei-Hsin TSENG ,  Jhen-Kai WANG

IPC: H03H17/00 ,  H03H7/25 ,  H03H11/24

CPC classification number: H03H17/0054 ,  H03H7/25 ,  H03H11/24

Abstract: A multi-level digital step attenuator (DSA) with a hybrid attenuation circuit is shown. The hybrid attenuation circuit is coupled between an input node and an output node of the multi-level DSA. The bypass switch of the multi-level DSA is controlled to provide a bypass path between the input node and the output node of the of the multi-level DSA when the hybrid attenuation circuit is in a disabled state. In the first active state, the hybrid attenuation circuit is switched to form a T-type structure to provide a first amount of signal attenuation. In the second active state, the hybrid attenuation circuit is switched to form a Pi-type structure to provide a second amount of signal attenuation.

公开(公告)号：US11742832B2

公开(公告)日：2023-08-29

申请号：US17727856

申请日：2022-04-25

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： Chien-Hui Tsai ,  Hung-Chen Chu ,  Yung-Tai Chen

IPC: H03K19/00 ,  H03H11/28 ,  H03H11/24

CPC classification number: H03H11/28 ,  H03H11/245 ,  H03K19/0005

Abstract: A transmission-end impedance matching circuit operates according to a signal of an overvoltage signal source and includes a first level shifter, a voltage generating circuit, and an impedance matching circuit. The first level shifter generates a first conversion voltage according to a source signal and operates between a first high voltage and a ground voltage. The voltage generating circuit generates a second high voltage according to the first conversion voltage, the first high voltage, and a medium voltage. The impedance matching circuit includes a second level shifter, a transistor, and two resistors. The second level shifter generates a gate voltage according to the second high voltage, a low voltage, and an input signal. The transistor is turned on/off according to the gate voltage and has a withstand voltage lower than the first high voltage. Each of the two resistors is coupled between the transistor and a differential signal transmission end.

公开(公告)号：US20230223927A1

公开(公告)日：2023-07-13

申请号：US18096171

申请日：2023-01-12

Applicant: Kumu Networks, Inc.

Inventor： Wilhelm Steffen Hahn

IPC: H03H9/54 ,  H03H11/16 ,  H03H11/26 ,  H03H11/24

CPC classification number: H03H9/54 ,  H03H11/16 ,  H03H11/26 ,  H03H11/24 ,  H03H9/02102

Abstract: A system for filter enhancement, preferably including one or more analog taps and a controller, and optionally including one or more couplers. The system is preferably configured to integrate with a filter, such as a passband filter or other frequency-based filter. The system can be configured to integrate with an RF communication system, an RF front end, or any other suitable RF circuitry. A method for filter enhancement, preferably including configuring one or more analog taps, and optionally including calibrating a system for filter enhancement and/or receiving temperature information.

公开(公告)号：US20230198491A1

公开(公告)日：2023-06-22

申请号：US18082360

申请日：2022-12-15

Applicant: pSemi Corporation

Inventor： Vikas Sharma ,  Peter Bacon

IPC: H03H7/25 ,  H03H11/24 ,  H03K17/687 ,  H03H11/20 ,  H03H7/20

CPC classification number: H03H7/25 ,  H03H11/245 ,  H03K17/687 ,  H03H11/20 ,  H03H7/20

Abstract: Digital step attenuator (DSA) and digital phase shifter (DPS) multi-stage circuit architectures that provide for high resolution. Embodiments use a dithering approach to weight bit positions to provide a much finer resolution than the lowest-valued individual stage. Bit position weights for stages are determined so as to enable selection of combinations of n bit positions that provide a desired total attenuation or phase shift range while allowing utilization of the large number of states (2n) available to produce fractional intermediate steps of attenuation or phase shift. The fractional intermediate steps have a resolution finer than the lowest-valued stage. Bit position weights may be determined using a weighting function, including weightings determined from a linear series, a geometric series, a harmonic series, or alternating variants of such series. In some embodiments, at least one bit position has a fixed value that is not determined by the bit position weighting function.

公开(公告)号：US11646720B2

公开(公告)日：2023-05-09

申请号：US17668225

申请日：2022-02-09

Applicant: Hong Kong Applied Science and Technology Research Institute Company Limited

Inventor： Danting Xu ,  Kun Wu ,  Ziyang Gao

IPC: H03H11/04 ,  H03H7/01 ,  H03H11/44 ,  H03H11/24 ,  H02M1/44 ,  H02M1/12

CPC classification number: H03H11/04 ,  H02M1/123 ,  H02M1/44 ,  H03H7/0115 ,  H03H11/245 ,  H03H11/44 ,  H03H2011/0483

Abstract: An active filter reduces Electro-Magnetic Interference (EMI) created by current flowing through a power line. The active filter connects to the power line at a single node through a connection capacitor. A sense current flows through the connection capacitor when the power line current changes. This sense current is applied to a gain control circuit having cross-coupled PNP transistors that drive currents to both terminals of a variable capacitor. The variable capacitor converts these currents to a voltage that is injected back into the power line through the connection capacitor as an injected compensation voltage that compensates for the sensed current.

公开(公告)号：US11533037B2

公开(公告)日：2022-12-20

申请号：US17115368

申请日：2020-12-08

Applicant: pSemi Corporation

Inventor： Vikas Sharma ,  Peter Bacon

IPC: H03H11/20 ,  H03H7/25 ,  H03H11/24 ,  H03K17/687 ,  H03H7/20

Abstract: Digital step attenuator (DSA) and digital phase shifter (DPS) multi-stage circuit architectures that provide for high resolution. Embodiments use a dithering approach to weight bit positions to provide a much finer resolution than the lowest-valued individual stage. Bit position weights for stages are determined so as to enable selection of combinations of n bit positions that provide a desired total attenuation or phase shift range while allowing utilization of the large number of states (2n) available to produce fractional intermediate steps of attenuation or phase shift. The fractional intermediate steps have a resolution finer than the lowest-valued stage. Bit position weights may be determined using a weighting function, including weightings determined from a linear series, a geometric series, a harmonic series, or alternating variants of such series. In some embodiments, at least one bit position has a fixed value that is not determined by the bit position weighting function.

公开(公告)号：US11522524B2

公开(公告)日：2022-12-06

申请号：US17503721

申请日：2021-10-18

Applicant: pSemi Corporation

Inventor： Peter Bacon

IPC: H03H11/24

Abstract: A programmable voltage variable attenuator (VVA) that enables selection among multiple analog, continuous attenuation ranges. Some embodiments include a dual-mode interface to enable digitally programming a DAC and provide the analog output to control the attenuation level of the VVA, or alternatively apply an externally provided analog voltage to directly control the VVA attenuation level. A VVA may be used in conjunction with a digital step attenuator (DSA). Some embodiments include circuitry for changing the VVA reference impedance. The attenuator architecture of the VVA includes one or more variable resistance shunt elements and/or series elements which may be a resistor and FET circuit controlled by a provided variable analog voltage. The multiple resistance element architecture may be implemented with stacked FET devices. Embodiments for the VVA may be based, for example, on T-type, Bridged-T type, Pi-type, L-pad type, reflection type, or balanced coupler type attenuators.