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    Semiconductor device processing method for material removal
    2.
    发明授权
    Semiconductor device processing method for material removal 有权

    公开(公告)号：US10600652B2

    公开(公告)日：2020-03-24

    申请号：US15485043

    申请日：2017-04-11

    申请人： DECA Technologies Inc.

    发明人： Timothy L. Olson ,  William Boyd Rogers ,  Ferdinand Aldas

    IPC分类号： H01L21/306 ,  H01L21/677 ,  H01L21/302 ,  H01L21/461 ,  H01L23/00 ,  H01L21/56

    摘要： A method of removing at least a portion of a layer of material from over a semiconductor substrate that can include dispensing an etching solution over the semiconductor substrate to form a pool of etching solution on the layer of material, wherein a footprint of the pool of etching solution is less than a footprint of the semiconductor substrate. The pool of etching solution and the semiconductor substrate can be moved with respect to each other. A pool boundary of the pool of etching solution can be defined on the semiconductor substrate with at least one air-knife such that the pool of etching solution etches the layer of material over the semiconductor substrate within the footprint of the pool of etching solution. The etching solution and at least a portion of the layer of material etched by the etching solution can be removed with the at least one air-knife.

    Fully molded peripheral package on package device
    3.
    发明授权
    Fully molded peripheral package on package device 有权

    公开(公告)号：US10050004B2

    公开(公告)日：2018-08-14

    申请号：US15356208

    申请日：2016-11-18

    申请人： DECA Technologies Inc.

    发明人： Christopher M. Scanlan ,  William Boyd Rogers ,  Craig Bishop

    IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/373 ,  H01L23/538 ,  H01L21/683 ,  H01L23/31 ,  H01L25/10

    摘要： A method of making a semiconductor device can comprise providing a temporary carrier comprising a semiconductor die mounting site, and forming an insulating layer over the temporary carrier. Conductive pads can be formed within openings in the insulating layer and be positioned both within and without the die mounting area. A backside redistribution layer (RDL) can be formed over the temporary carrier before mounting a semiconductor die at the die mounting site. Conductive interconnects can be formed over the temporary carrier in a periphery of the semiconductor die mounting site. A semiconductor die can be mounted face up to the insulating layer. The conductive interconnects, backside RDL, and semiconductor die can be encapsulated with a mold compound. A build-up interconnect structure can be formed and connected to the semiconductor die and the conductive interconnects. The temporary carrier can be removed and the conductive pads exposed in a grinding process.

    Semiconductor device and method of land grid array packaging with bussing lines
    6.
    发明授权
    Semiconductor device and method of land grid array packaging with bussing lines 有权
    集线器阵列阵列封装半导体器件及方法

    公开(公告)号：US09269622B2

    公开(公告)日：2016-02-23

    申请号：US13891056

    申请日：2013-05-09

    申请人： DECA Technologies Inc.

    发明人： Christopher M. Scanlan ,  Timothy L. Olson

    IPC分类号： H01L21/78 ,  H01L23/00 ,  H01L21/56

    CPC分类号： H01L21/78 ,  H01L21/568 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00

    摘要： A semiconductor device and method of making a semiconductor device is described. An embedded die panel comprising a plurality of semiconductor die separated by saw streets is provided. A conductive layer is formed by an electroless plating process, the conductive layer comprising bussing lines disposed in the saw streets and a redistribution layer (RDL) coupled to the semiconductor die and bussing lines. An insulating layer is formed over the conductive layer and embedded die panel, the insulating layer comprising openings disposed over the conductive layer outside a footprint of the semiconductor die. Interconnect structures are formed in the openings in the insulating layer by using the conductive layer as part of an electroplating process. The embedded die panel is singulated through the saw streets after forming the interconnect structures to remove the bussing lines and to from individual fan-out wafer level packages (FOWLPs).

    摘要翻译： 描述制造半导体器件的半导体器件和方法。 提供了一种嵌入式模具面板，其包括由锯片隔开的多个半导体模具。 通过化学镀处理形成导电层，导电层包括布置在锯条街道中的总线和耦合到半导体管芯和总线的再分配层（RDL）。 绝缘层形成在导电层和嵌入的模板上，绝缘层包括设置在半导体管芯的覆盖区外的导电层上的开口。 通过使用导电层作为电镀工艺的一部分，在绝缘层的开口中形成互连结构。 在形成互连结构之后，将嵌入式模具面板通过锯条划分，以去除总线和来自各个扇出的晶片级封装（FOWLP）。