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    Low cost fabrication method for high voltage, high drain current MOS transistor
    1.
    发明申请
    Low cost fabrication method for high voltage, high drain current MOS transistor 有权
    低成本高漏极电流MOS晶体管制造方法

    公开(公告)号：US20050118753A1

    公开(公告)日：2005-06-02

    申请号：US10725642

    申请日：2003-12-02

    申请人： Taylor Efland ,  Jozef Mitros ,  Imran Khan

    发明人： Taylor Efland ,  Jozef Mitros ,  Imran Khan

    IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

    CPC分类号： H01L29/0847 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

    摘要： A method for reducing the drain resistance of a drain-extended MOS transistor in a semiconductor wafer, while maintaining a high transistor breakdown voltage. The method provides a first well (502) of a first conductivity type, operable as the extension of the transistor drain (501) of the first conductivity type; portions of the well are covered by a first insulator (503) having a first thickness. A second well (504) of the opposite conductivity type is intended to contain the transistor source (506) of the first conductivity type; portions of the second well are covered by a second insulator (507) thinner than the first insulator. The first and second wells form a junction (505) that terminates at the second insulator (530a, 530b). The method deposits a photoresist layer (510) over the wafer, which is patterned by opening a window (510a) that extends from the drain to the junction termination. Next, ions (540) of the first conductivity type are implanted through the window into the first well; these said ions have an energy to limit the penetration depth (541) to the first insulator thickness, and a dose to create a well region (560) of high doping concentration adjacent to the junction termination (530a).

    摘要翻译： 一种在保持高晶体管击穿电压的同时降低半导体晶片中的漏极扩展MOS晶体管的漏极电阻的方法。 该方法提供第一导电类型的第一阱（50​​2），其可操作为第一导电类型的晶体管漏极（501）的延伸; 阱的一部分被具有第一厚度的第一绝缘体（503）覆盖。 相反导电类型的第二阱（504）旨在包含第一导电类型的晶体管源（506）; 第二阱的部分被比第一绝缘体薄的第二绝缘体（507）覆盖。 第一和第二阱形成终止于第二绝缘体（530a，530b）的结（505）。 该方法将光致抗蚀剂层（510）沉积在晶片之上，其通过打开从漏极延伸到结终端的窗口（510a）而被图案化。 接下来，通过窗口将第一导电类型的离子（540）注入到第一阱中; 这些所述离子具有将穿透深度（541）限制到第一绝缘体厚度的能量，以及用于产生邻近连接终端（530a）的高掺杂浓度的阱区（560）的剂量。

    Robust DEMOS transistors and method for making the same
    2.
    发明申请
    Robust DEMOS transistors and method for making the same 有权
    坚固的DEMOS晶体管及其制造方法

    公开(公告)号：US20050253191A1

    公开(公告)日：2005-11-17

    申请号：US10837918

    申请日：2004-05-03

    申请人： Sameer Pendharkar ,  Ramanathan Ramani ,  Taylor Efland

    发明人： Sameer Pendharkar ,  Ramanathan Ramani ,  Taylor Efland

    IPC分类号： H01L21/336 ,  H01L29/08 ,  H01L29/10 ,  H01L29/76 ,  H01L29/78

    CPC分类号： H01L29/0847 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/7835

    摘要： Extended-drain MOS transistor devices and fabrication methods are provided, in which a drift region of a first conductivity type is formed between a drain of the first conductivity type and a channel. The drift region comprises first and second portions, the first portion extending partially under a gate structure between the channel and the second portion, and the second portion extending laterally between the first portion and the drain, wherein the first portion of the drift region has a concentration of first type dopants higher than the second portion.

    摘要翻译： 提供了扩大漏极MOS晶体管器件和制造方法，其中在第一导电类型的漏极和沟道之间形成第一导电类型的漂移区域。 所述漂移区域包括第一和第二部分，所述第一部分部分地在所述通道和所述第二部分之间的栅极结构下方延伸，并且所述第二部分在所述第一部分和所述漏极之间横向延伸，其中所述漂移区域的所述第一部分具有 第一种掺杂剂的浓度高于第二部分。

    Lateral double diffused metal oxide semiconductor device
    3.
    发明授权
    Lateral double diffused metal oxide semiconductor device 有权

    公开(公告)号：US06441431B1

    公开(公告)日：2002-08-27

    申请号：US09454934

    申请日：1999-12-03

    申请人： Taylor Efland ,  Chin-Yu Tsai ,  Sameer Pendharkar

    发明人： Taylor Efland ,  Chin-Yu Tsai ,  Sameer Pendharkar

    IPC分类号： H01L2976

    CPC分类号： H01L29/66537 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7816 ,  H01L29/7833

    摘要： An embodiment of the instant invention is a transistor formed on a semiconductor substrate of a first conductivity type and having an upper surface, the transistor comprising: a well region (well 204 of FIG. 1a) formed in the semiconductor substrate (layer 202 of FIG. 1a), the well region of a second conductivity type opposite that of the first conductivity type; a source region (source region 208 of FIG. 1a) formed in the well region in the semiconductor substrate, the source region of the second conductivity type; a drain region (drain 210 of FIG. 1a) formed in the semiconductor substrate and spaced away from the source region by a channel region (given by length L1+L2), the drain region of the second conductivity type; a conductive gate electrode (layer 218 of FIG. 1a) disposed over the semiconductor substrate and over the channel region; a gate insulating layer (layer 214 of FIG. 1a) disposed between the conductive gate electrode and the semiconductor substrate and having a length, the gate insulating layer comprising: a first portion of the gate insulating layer which has a first length (L1) and a first thickness; a second portion of the gate insulating layer which has a second length (L2) and a second thickness which is substantially thicker than the first thickness, the sum of the first length and the second length equalling the length of the gate insulating layer; and wherein the first portion of the gate insulating layer being situated proximate to the source region and spaced away from the drain region by the second portion of the gate insulating layer; and wherein the well region having a dopant concentration less than that of the source region and the drain region, the well region extends at least from source region towards the drain region so as to completely underlie the first portion of the gate insulating layer and to underlie at least the second portion of the gate insulating layer.

    POWER INTEGRATED CIRCUIT INCLUDING SERIES-CONNECTED SOURCE SUBSTRATE AND DRAIN SUBSTRATE POWER MOSFETS
    9.
    发明申请
    POWER INTEGRATED CIRCUIT INCLUDING SERIES-CONNECTED SOURCE SUBSTRATE AND DRAIN SUBSTRATE POWER MOSFETS 有权
    功率集成电路，包括串联源极基极和漏极基极功率MOSFET

    公开(公告)号：US20140197486A1

    公开(公告)日：2014-07-17

    申请号：US13563923

    申请日：2012-08-01

    申请人： Christopher Boguslaw Kocon ,  Marie Denison ,  Taylor Efland

    发明人： Christopher Boguslaw Kocon ,  Marie Denison ,  Taylor Efland

    IPC分类号： H01L27/088 ,  H01L29/78

    CPC分类号： H01L27/088 ,  H01L27/0922 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/7802 ,  H01L29/7803 ,  H01L29/7809 ,  H01L29/7816 ,  H01L29/7835

    摘要： A semiconductor device containing a high voltage MOS transistor with a drain drift region over a lower drain layer and channel regions laterally disposed at the top surface of the substrate. RESURF trenches cut through the drain drift region and body region parallel to channel current flow. The RESURF trenches have dielectric liners and electrically conductive RESURF elements on the liners. Source contact metal is disposed over the body region and source regions. A semiconductor device containing a high voltage MOS transistor with a drain drift region over a lower drain layer, and channel regions laterally disposed at the top surface of the substrate. RESURF trenches cut through the drain drift region and body region perpendicular to channel current flow. Source contact metal is disposed in a source contact trench and extended over the drain drift region to provide a field plate.

    摘要翻译： 一种半导体器件，其包含在下漏极层上方具有漏极漂移区域的高电压MOS晶体管和横向设置在衬底顶表面处的沟道区域。 RESURF沟槽穿过漏极漂移区域和与通道电流流动平行的体区域。 RESURF沟槽在衬垫上具有电介质衬垫和导电RESURF元件。 源接触金属设置在身体区域和源区域上。 一种半导体器件，其包含在下漏极层上具有漏极漂移区域的高电压MOS晶体管，以及横向设置在衬底顶表面处的沟道区域。 RESURF沟槽穿过垂直于沟道电流的漏极漂移区域和体区。 源极接触金属设置在源极接触沟槽中并在漏极漂移区域上延伸以提供场板。