公开(公告)号：US20060113592A1

公开(公告)日：2006-06-01

申请号：US11325165

申请日：2006-01-04

申请人： Sameer Pendharkar ,  Ramanathan Ramani ,  Taylor Efland

发明人： Sameer Pendharkar ,  Ramanathan Ramani ,  Taylor Efland

IPC分类号： H01L29/76

CPC分类号： H01L29/0847 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/7835

摘要： Extended-drain MOS transistor devices and fabrication methods are provided, in which a drift region of a first conductivity type is formed between a drain of the first conductivity type and a channel. The drift region comprises first and second portions, the first portion extending partially under a gate structure between the channel and the second portion, and the second portion extending laterally between the first portion and the drain, wherein the first portion of the drift region has a concentration of first type dopants higher than the second portion.

公开(公告)号：US20050253191A1

公开(公告)日：2005-11-17

申请号：US10837918

申请日：2004-05-03

申请人： Sameer Pendharkar ,  Ramanathan Ramani ,  Taylor Efland

发明人： Sameer Pendharkar ,  Ramanathan Ramani ,  Taylor Efland

IPC分类号： H01L21/336 ,  H01L29/08 ,  H01L29/10 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L29/0847 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/7835

摘要： Extended-drain MOS transistor devices and fabrication methods are provided, in which a drift region of a first conductivity type is formed between a drain of the first conductivity type and a channel. The drift region comprises first and second portions, the first portion extending partially under a gate structure between the channel and the second portion, and the second portion extending laterally between the first portion and the drain, wherein the first portion of the drift region has a concentration of first type dopants higher than the second portion.

摘要翻译： 提供了扩大漏极MOS晶体管器件和制造方法，其中在第一导电类型的漏极和沟道之间形成第一导电类型的漂移区域。 所述漂移区域包括第一和第二部分，所述第一部分部分地在所述通道和所述第二部分之间的栅极结构下方延伸，并且所述第二部分在所述第一部分和所述漏极之间横向延伸，其中所述漂移区域的所述第一部分具有 第一种掺杂剂的浓度高于第二部分。

公开(公告)号：US07514329B2

公开(公告)日：2009-04-07

申请号：US11325165

申请日：2006-01-04

申请人： Sameer Pendharkar ,  Ramanathan Ramani ,  Taylor R. Efland

发明人： Sameer Pendharkar ,  Ramanathan Ramani ,  Taylor R. Efland

IPC分类号： H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/7835

摘要： Extended-drain MOS transistor devices and fabrication methods are provided, in which a drift region of a first conductivity type is formed between a drain of the first conductivity type and a channel. The drift region comprises first and second portions, the first portion extending partially under a gate structure between the channel and the second portion, and the second portion extending laterally between the first portion and the drain, wherein the first portion of the drift region has a concentration of first type dopants higher than the second portion.

摘要翻译： 提供了扩大漏极MOS晶体管器件和制造方法，其中在第一导电类型的漏极和沟道之间形成第一导电类型的漂移区域。 所述漂移区域包括第一和第二部分，所述第一部分部分地在所述通道和所述第二部分之间的栅极结构下方延伸，并且所述第二部分在所述第一部分和所述漏极之间横向延伸，其中所述漂移区域的所述第一部分具有 第一种掺杂剂的浓度高于第二部分。

公开(公告)号：US07238986B2

公开(公告)日：2007-07-03

申请号：US10837918

申请日：2004-05-03

申请人： Sameer Pendharkar ,  Ramanathan Ramani ,  Taylor R. Efland

发明人： Sameer Pendharkar ,  Ramanathan Ramani ,  Taylor R. Efland

IPC分类号： H01L29/76

CPC分类号： H01L29/0847 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/7835

摘要： Extended-drain MOS transistor devices and fabrication methods are provided, in which a drift region of a first conductivity type is formed between a drain of the first conductivity type and a channel. The drift region comprises first and second portions, the first portion extending partially under a gate structure between the channel and the second portion, and the second portion extending laterally between the first portion and the drain, wherein the first portion of the drift region has a concentration of first type dopants higher than the second portion.

摘要翻译： 提供了扩大漏极MOS晶体管器件和制造方法，其中在第一导电类型的漏极和沟道之间形成第一导电类型的漂移区域。 所述漂移区域包括第一和第二部分，所述第一部分部分地在所述通道和所述第二部分之间的栅极结构下方延伸，并且所述第二部分在所述第一部分和所述漏极之间横向延伸，其中所述漂移区域的所述第一部分具有 第一种掺杂剂的浓度高于第二部分。

公开(公告)号：US06770935B2

公开(公告)日：2004-08-03

申请号：US10166965

申请日：2002-06-11

申请人： Taylor R. Efland ,  David A. Grant ,  Ramanathan Ramani ,  Chin-Yu Tsai ,  Dale Skelton

发明人： Taylor R. Efland ,  David A. Grant ,  Ramanathan Ramani ,  Chin-Yu Tsai ,  Dale Skelton

IPC分类号： H01L2701

CPC分类号： H01L21/761 ,  H01L21/765 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/7835

摘要： An array (90) of transistors (50) formed in a p-type layer (34), and including a second heavily doped p-type region (56) laterally extending proximate the drain of each transistor to collect minority carriers of the transistors. A deep n-type region (16) is formed in the p-type layer (34) and proximate a n-type buried layer (14) together forming a guardring about the drain regions of the plurality of transistors. The array of transistors may be interconnected in parallel to form a large power FET, whereby the heavily doped second p-type region (56) reduces the minority carrier lifetime proximate the drains of the transistors. The guardring (14, 16) collects the minority carriers (T1) and is isolated from the drains of the transistors. Preferably, the transistors are formed in a P-epi tank that is isolated by the guardring. The P-epi tank is preferably formed upon a buried NBL layer, and the deep n-type region is an N+ well extending to the buried NBL layer. The guardring is preferably grounded when utilized as the low side transistor to collect minority carriers.

摘要翻译： 形成在p型层（34）中的晶体管（50）的阵列（90），并且包括在每个晶体管的漏极附近横向延伸以收集晶体管的少数载流子的第二重掺杂p型区域（56）。 在p型层（34）中形成深n型区域（16）并邻近n型掩埋层（14），形成围绕多个晶体管的漏极区域的保护。 晶体管阵列可以并联连接以形成大功率FET，由此重掺杂的第二p型区域（56）减少了靠近晶体管漏极的少数载流子寿命。 防护（14,16）收集少数载流子（T1），并与晶体管的漏极隔离。 优选地，晶体管形成在由护罩隔离的P-epi罐中。 P-epi罐优选地形成在掩埋NBL层上，并且深n型区域是延伸到掩埋NBL层的N +阱。 当用作低侧晶体管以收集少数载流子时，护罩优选地接地。

公开(公告)号：US06710427B2

公开(公告)日：2004-03-23

申请号：US10167136

申请日：2002-06-11

申请人： Taylor R. Efland ,  David A. Grant ,  Ramanathan Ramani ,  Chin-Yu Tsai ,  David D. Briggs ,  Dale Skelton

发明人： Taylor R. Efland ,  David A. Grant ,  Ramanathan Ramani ,  Chin-Yu Tsai ,  David D. Briggs ,  Dale Skelton

IPC分类号： H01L2900

CPC分类号： H01L29/1083 ,  H01L21/761 ,  H01L21/765 ,  H01L29/1045 ,  H01L29/7835

摘要： A distributed power device (100) including a plurality of tank regions (90) separated from one another by a deep n-type region (16), and having formed in each tank region a plurality of transistors (50). The plurality of transistors (50) in each tank region are interconnected to transistors in other tank regions to form a large power FET, whereby the deep n-type regions isolate the tank regions from one another. A first parasitic diode (D5) is defined from each tank region to a buried layer, and a second parasitic diode (D4) is defined between the buried layer and a substrate. The deep n-type regions distribute the first and second parasitic diodes with respect to the plurality of tank regions, preferably comprised of a P-epi tank. The deep n-type regions also distribute the resistance of an NBL layer (14) formed under the tank regions. The distributed parasitic diodes and resistance of the NBL layer advantageously provides that the parasitic diode (D4) between the NBL layer and the substrate will never be forward biased. In addition, each of the tank regions has a heavily doped p-type region (56) reducing the minority carrier lifetime to provide increased switching speed of the large power FET.

摘要翻译： 一种分布式功率器件（100），包括通过深n型区域（16）彼此分离的多个槽区（90），并且在每个槽区中形成有多个晶体管（50）。 每个槽区中的多个晶体管（50）与其它罐区中的晶体管相互连接以形成大功率FET，由此深n型区域将罐区彼此隔离。 第一寄生二极管（D5）从每个槽区限定到埋层，并且在掩埋层和衬底之间限定第二寄生二极管（D4）。 深n型区域相对于多个罐区域分布第一和第二寄生二极管，优选地由P-epi罐组成。 深n型区域还分布形成在罐区域下方的NBL层（14）的电阻。 分布式寄生二极管和NBL层的电阻有利地提供NBL层和衬底之间的寄生二极管（D4）将永远不会被正向偏置。 此外，每个槽区具有重掺杂的p型区（56），减少了少量载流子寿命，以提供大功率FET的提高的开关速度。

公开(公告)号：US06784493B2

公开(公告)日：2004-08-31

申请号：US10166956

申请日：2002-06-11

申请人： Taylor R. Efland ,  David A. Grant ,  Ramanathan Ramani ,  Dale Skelton ,  David D. Briggs ,  Chin-Yu Tsai

发明人： Taylor R. Efland ,  David A. Grant ,  Ramanathan Ramani ,  Dale Skelton ,  David D. Briggs ,  Chin-Yu Tsai

IPC分类号： H01L2900

CPC分类号： H01L29/7835 ,  H01L21/761 ,  H01L21/765 ,  H01L29/1045 ,  H01L29/1083

摘要： A power integrated circuit architecture (10) having a high side transistor (100) interposed between a control circuit (152) and a low side transistor (100) to reduce the effects of the low side transistor on the operation of the control circuit. The low side transistor has a heavily p-doped region (56) designed to reduce minority carrier lifetime and improve minority carrier collection to reduce the minority carriers from disturbing the control circuit. The low side transistor has a guardring (16) tied to an analog ground, whereby the control circuit is tied to a digital ground, such that the collection of the minority carriers into the analog ground does not disturb the operation of the control circuit. The low side transistor is comprised of multiple transistor arrays (90) partitioned by at least one deep n-type region (16), which deep n-type region forms a guardring about the respective transistor array. The guardring isolates minority carriers in one transistor array from another transistor array, and facilitates the collection of the minority carriers therethrough.

摘要翻译： 一种功率集成电路架构（10），其具有插入在控制电路（152）和低侧晶体管（100）之间的高侧晶体管（100），以降低所述低侧晶体管对所述控制电路的操作的影响。 低侧晶体管具有高p掺杂区域（56），其被设计为减少少数载流子寿命并改善少数载流子收集以减少少数载流子扰乱控制电路。 低侧晶体管具有被连接到模拟地的保护（16），由此将控制电路连接到数字地，使得将少数载流子收集到模拟地中不会干扰控制电路的操作。 低侧晶体管包括由至少一个深n型区域（16）分隔的多个晶体管阵列（90），该深n型区域围绕相应的晶体管阵列形成保护。 防护器将一个晶体管阵列中的少数载流子与另一晶体管阵列隔离，并且便于通过其中的少数载流子的收集。

公开(公告)号：US06709900B2

公开(公告)日：2004-03-23

申请号：US10166964

申请日：2002-06-11

申请人： Taylor R. Efland ,  David A. Grant ,  Ramanathan Ramani ,  Dale Skelton ,  David D. Briggs ,  Chin-Yu Tsai

发明人： Taylor R. Efland ,  David A. Grant ,  Ramanathan Ramani ,  Dale Skelton ,  David D. Briggs ,  Chin-Yu Tsai

IPC分类号： H01L21332

CPC分类号： H01L29/1083 ,  H01L21/761 ,  H01L21/765 ,  H01L29/1045 ,  H01L29/7835

摘要： A power integrated circuit architecture (10) having a high side transistor (100) interposed between a control circuit (152) and a low side transistor (100) to reduce the effects of the low side transistor on the operation of the control circuit. The low side transistor has a heavily p-doped region (56) designed to reduce minority carrier lifetime and improve minority carrier collection to reduce the minority carriers from disturbing the control circuit. The low side transistor has a guardring (16) tied to an analog ground, whereby the control circuit is tied to a digital ground, such that the collection of the minority carriers into the analog ground does not disturb the operation of the control circuit. The low side transistor is comprised of multiple transistor arrays (90) partitioned by at least one deep n-type region (16), which deep n-type region forms a guardring about the respective transistor array. The guardring isolates minority carriers in one transistor array from another transistor array, and facilitates the collection of the minority carriers therethrough.

摘要翻译： 一种功率集成电路架构（10），其具有插入在控制电路（152）和低侧晶体管（100）之间的高侧晶体管（100），以降低所述低侧晶体管对所述控制电路的操作的影响。 低侧晶体管具有高p掺杂区域（56），其被设计为减少少数载流子寿命并改善少数载流子收集以减少少数载流子扰乱控制电路。 低侧晶体管具有被连接到模拟地的保护（16），由此将控制电路连接到数字地，使得将少数载流子收集到模拟地中不会干扰控制电路的操作。 低侧晶体管包括由至少一个深n型区域（16）分隔的多个晶体管阵列（90），该深n型区域围绕相应的晶体管阵列形成保护。 防护器将一个晶体管阵列中的少数载流子与另一晶体管阵列隔离，并且便于通过其中的少数载流子的收集。