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    System for high-precision double-diffused MOS transistors
    2.
    发明申请
    System for high-precision double-diffused MOS transistors 审中-公开
    高精度双扩散MOS晶体管系统

    公开(公告)号：US20050127409A1

    公开(公告)日：2005-06-16

    申请号：US11042536

    申请日：2005-01-25

    申请人： Henry Edwards ,  Sameer Pendharkar ,  Joe Trogolo ,  Tathagata Chatterjee ,  Taylor Efland

    发明人： Henry Edwards ,  Sameer Pendharkar ,  Joe Trogolo ,  Tathagata Chatterjee ,  Taylor Efland

    IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76 ,  H01L21/336 ,  H01L31/062

    CPC分类号： H01L29/0696 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/7801

    摘要： The present invention provides a system for efficiently producing versatile, high-precision MOS device structures in which straight regions dominate the device's behavior, providing minimum geometry devices that precisely match large devices, in an easy, efficient and cost-effective manner. The present invention provides methods and apparatus for producing double diffused semiconductor devices that minimize performance impacts of end cap regions. The present invention provides a MOS structure having a moat region (404, 516, 616), and an oxide region (414, 512, 608) overlapping the moat region. A double-diffusion region (402, 504, 618) is formed within the oxide region, having end cap regions (406, 502, 620) that are effectively deactivated utilizing geometric and implant manipulations.

    摘要翻译： 本发明提供了一种用于有效地生产多功能，高精度的MOS器件结构的系统，其中直线区域主导器件的行为，以简单，高效和成本有效的方式提供精确匹配大型器件的最小几何器件。 本发明提供了用于生产双扩散半导体器件的方法和装置，其最小化端帽区域的性能影响。 本发明提供一种MOS结构，其具有护城河区域（404,516,616）和与护城河区域重叠的氧化物区域（414,512,608）。 在氧化物区域内形成双扩散区域（402,504,618），具有端盖区域（406,502,620），其可以利用几何和植入操作被有效地去激活。

    System for high-precision double-diffused MOS transistors
    3.
    发明授权
    System for high-precision double-diffused MOS transistors 有权
    高精度双扩散MOS晶体管系统

    公开(公告)号：US06867100B2

    公开(公告)日：2005-03-15

    申请号：US10326214

    申请日：2002-12-19

    申请人： Henry L. Edwards ,  Sameer Pendharkar ,  Joe Trogolo ,  Tathagata Chatterjee ,  Taylor Efland

    发明人： Henry L. Edwards ,  Sameer Pendharkar ,  Joe Trogolo ,  Tathagata Chatterjee ,  Taylor Efland

    IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/0696 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/7801

    摘要： The present invention provides a system for efficiently producing versatile, high-precision MOS device structures in which straight regions dominate the device's behavior, providing minimum geometry devices that precisely match large devices, in an easy, efficient and cost-effective manner. The present invention provides methods and apparatus for producing double diffused semiconductor devices that minimize performance impacts of end cap regions. The present invention provides a MOS structure having a moat region (404, 516, 616), and an oxide region (414, 512, 608) overlapping the moat region. A double-diffusion region (402, 504, 618) is formed within the oxide region, having end cap regions (406, 502, 620) that are effectively deactivated utilizing geometric and implant manipulations.

    摘要翻译： 本发明提供了一种用于有效地生产多功能，高精度的MOS器件结构的系统，其中直线区域主导器件的行为，以简单，高效和成本有效的方式提供精确匹配大型器件的最小几何器件。 本发明提供了用于生产双扩散半导体器件的方法和装置，其最小化端帽区域的性能影响。 本发明提供一种MOS结构，其具有护城河区域（404,516,616）和与护城河区域重叠的氧化物区域（414,512,608）。 在氧化物区域内形成双扩散区域（402,504,618），具有端盖区域（406,502,620），其可以利用几何和植入操作被有效地去激活。

    Robust DEMOS transistors and method for making the same
    4.
    发明申请
    Robust DEMOS transistors and method for making the same 有权
    坚固的DEMOS晶体管及其制造方法

    公开(公告)号：US20050253191A1

    公开(公告)日：2005-11-17

    申请号：US10837918

    申请日：2004-05-03

    申请人： Sameer Pendharkar ,  Ramanathan Ramani ,  Taylor Efland

    发明人： Sameer Pendharkar ,  Ramanathan Ramani ,  Taylor Efland

    IPC分类号： H01L21/336 ,  H01L29/08 ,  H01L29/10 ,  H01L29/76 ,  H01L29/78

    CPC分类号： H01L29/0847 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/7835

    摘要： Extended-drain MOS transistor devices and fabrication methods are provided, in which a drift region of a first conductivity type is formed between a drain of the first conductivity type and a channel. The drift region comprises first and second portions, the first portion extending partially under a gate structure between the channel and the second portion, and the second portion extending laterally between the first portion and the drain, wherein the first portion of the drift region has a concentration of first type dopants higher than the second portion.

    摘要翻译： 提供了扩大漏极MOS晶体管器件和制造方法，其中在第一导电类型的漏极和沟道之间形成第一导电类型的漂移区域。 所述漂移区域包括第一和第二部分，所述第一部分部分地在所述通道和所述第二部分之间的栅极结构下方延伸，并且所述第二部分在所述第一部分和所述漏极之间横向延伸，其中所述漂移区域的所述第一部分具有 第一种掺杂剂的浓度高于第二部分。

    Lateral double diffused metal oxide semiconductor device
    5.
    发明授权
    Lateral double diffused metal oxide semiconductor device 有权

    公开(公告)号：US06441431B1

    公开(公告)日：2002-08-27

    申请号：US09454934

    申请日：1999-12-03

    申请人： Taylor Efland ,  Chin-Yu Tsai ,  Sameer Pendharkar

    发明人： Taylor Efland ,  Chin-Yu Tsai ,  Sameer Pendharkar

    IPC分类号： H01L2976

    CPC分类号： H01L29/66537 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7816 ,  H01L29/7833

    摘要： An embodiment of the instant invention is a transistor formed on a semiconductor substrate of a first conductivity type and having an upper surface, the transistor comprising: a well region (well 204 of FIG. 1a) formed in the semiconductor substrate (layer 202 of FIG. 1a), the well region of a second conductivity type opposite that of the first conductivity type; a source region (source region 208 of FIG. 1a) formed in the well region in the semiconductor substrate, the source region of the second conductivity type; a drain region (drain 210 of FIG. 1a) formed in the semiconductor substrate and spaced away from the source region by a channel region (given by length L1+L2), the drain region of the second conductivity type; a conductive gate electrode (layer 218 of FIG. 1a) disposed over the semiconductor substrate and over the channel region; a gate insulating layer (layer 214 of FIG. 1a) disposed between the conductive gate electrode and the semiconductor substrate and having a length, the gate insulating layer comprising: a first portion of the gate insulating layer which has a first length (L1) and a first thickness; a second portion of the gate insulating layer which has a second length (L2) and a second thickness which is substantially thicker than the first thickness, the sum of the first length and the second length equalling the length of the gate insulating layer; and wherein the first portion of the gate insulating layer being situated proximate to the source region and spaced away from the drain region by the second portion of the gate insulating layer; and wherein the well region having a dopant concentration less than that of the source region and the drain region, the well region extends at least from source region towards the drain region so as to completely underlie the first portion of the gate insulating layer and to underlie at least the second portion of the gate insulating layer.

    Integrated gate controlled high voltage divider
    8.
    发明授权
    Integrated gate controlled high voltage divider 有权
    集成门控高压分压器

    公开(公告)号：US08872273B2

    公开(公告)日：2014-10-28

    申请号：US13567340

    申请日：2012-08-06

    申请人： Hideaki Kawahara ,  Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower ,  John Lin ,  Robert A. Neidorff

    发明人： Hideaki Kawahara ,  Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower ,  John Lin ,  Robert A. Neidorff

    IPC分类号： H01L27/11 ,  H01L27/06 ,  H01L49/02

    CPC分类号： H01L28/20 ,  H01L27/0629

    摘要： An integrated circuit containing a gate controlled voltage divider having an upper resistor on field oxide in series with a transistor switch in series with a lower resistor. A resistor drift layer is disposed under the upper resistor, and the transistor switch includes a switch drift layer adjacent to the resistor drift layer, separated by a region which prevents breakdown between the drift layers. The switch drift layer provides an extended drain or collector for the transistor switch. A sense terminal of the voltage divider is coupled to a source or emitter node of the transistor and to the lower resistor. An input terminal is coupled to the upper resistor and the resistor drift layer. A process of forming the integrated circuit containing the gate controlled voltage divider.

    摘要翻译： 一种集成电路，其包含栅极控制分压器，该栅极控制分压器具有与场效应晶体管上的上电阻串联的晶体管开关，与下电阻串联。 电阻器漂移层设置在上电阻器下方，并且晶体管开关包括与电阻器漂移层相邻的开关漂移层，由防止漂移层之间的击穿的区域分开。 开关漂移层为晶体管开关提供了扩展的漏极或集电极。 分压器的感测端子耦合到晶体管的源极或发射极节点和下电阻器。 输入端子耦合到上电阻器和电阻漂移层。 形成包含栅极控制分压器的集成电路的工艺。

    PROGRAMMABLE SCR FOR LDMOS ESD PROTECTION
    9.
    发明申请
    PROGRAMMABLE SCR FOR LDMOS ESD PROTECTION 有权
    用于LDMOS ESD保护的可编程SCR

    公开(公告)号：US20130285137A1

    公开(公告)日：2013-10-31

    申请号：US13460523

    申请日：2012-04-30

    申请人： Sameer Pendharkar ,  Suhail Murtaza ,  Juergen Wittmann

    发明人： Sameer Pendharkar ,  Suhail Murtaza ,  Juergen Wittmann

    IPC分类号： H01L29/78

    CPC分类号： H01L29/0692 ,  H01L29/87

    摘要： A protection circuit for a DMOS transistor comprises an anode circuit having a first heavily doped region of a first conductivity type (314) formed within and electrically connected to a first lightly doped region of the second conductivity type (310, 312). A cathode circuit having a plurality of third heavily doped regions of the first conductivity type (700) within a second heavily doped region of the second conductivity type (304). A first lead (202) is connected to each third heavily doped region (704) and connected to the second heavily doped region by at least three spaced apart connections (702) between every two third heavily doped regions. An SCR (400, 402) is connected between the anode circuit and the cathode circuit. The DMOS transistor has a drain (310, 312, 316) connected to the anode circuit and a source (304) connected to the cathode circuit.

    摘要翻译： 用于DMOS晶体管的保护电路包括阳极电路，其具有在第二导电类型（310,312）的第一轻掺杂区域内形成并电连接的第一导电类型的第一重掺杂区域（314）。 在第二导电类型（304）的第二重掺杂区域内具有第一导电类型（700）的多个第三重掺杂区域的阴极电路。 第一引线（202）连接到每个第三重掺杂区域（704），并且通过每两个第三重掺杂区域之间的至少三个间隔开的连接（702）连接到第二重掺杂区域。 在阳极电路和阴极电路之间连接有SCR（400,402）。 DMOS晶体管具有连接到阳极电路的漏极（310,312,316）和连接到阴极电路的源极（304）。