公开(公告)号：US11764218B2

公开(公告)日：2023-09-19

申请号：US17353533

申请日：2021-06-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shun-Jang Liao ,  Chia-Chun Liao ,  Shu-Hui Wang ,  Shih-Hsun Chang

IPC: H01L27/092 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L21/28 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/49

CPC classification number: H01L27/0922 ,  H01L21/28088 ,  H01L21/76897 ,  H01L21/82345 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/785

Abstract: A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and a second first-type-channel FET including a second gate structure. The first first-type-channel FET has a smaller threshold voltage than the second first-type-channel FET. The first gate structure includes a first work function adjustment material (WFM) layer and the second gate structure includes a second WFM layer. At least one of thickness and material of the first and second WFM layers is different from each other.

公开(公告)号：US12166038B2

公开(公告)日：2024-12-10

申请号：US18224487

申请日：2023-07-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shun-Jang Liao ,  Chia-Chun Liao ,  Shu-Hui Wang ,  Shih-Hsun Chang

IPC: H01L27/092 ,  H01L21/28 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/49 ,  H01L29/78

Abstract: A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and a second first-type-channel FET including a second gate structure. The first first-type-channel FET has a smaller threshold voltage than the second first-type-channel FET. The first gate structure includes a first work function adjustment material (WFM) layer and the second gate structure includes a second WFM layer. At least one of thickness and material of the first and second WFM layers is different from each other.

公开(公告)号：US20190280097A1

公开(公告)日：2019-09-12

申请号：US16416465

申请日：2019-05-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hua Feng Chen ,  Shu-Hui Wang ,  Mu-Chi Chiang

IPC: H01L29/43 ,  H01L29/16 ,  H01L49/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/161 ,  H01L27/06 ,  H01L29/49 ,  H01L29/66 ,  H01L29/165

Abstract: A semiconductor structure can include a resistor on a substrate formed simultaneously with other devices, such as transistors. A diffusion barrier layer formed on a substrate is patterned to form a resistor and barrier layers under a transistor gate. A filler material, a first connector, and a second connector are formed on the resistor at the same manner and time as the gate of the transistor. The filler material is removed to form a resistor on a substrate.

公开(公告)号：US10297669B2

公开(公告)日：2019-05-21

申请号：US15351139

申请日：2016-11-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hua Feng Chen ,  Shu-Hui Wang ,  Mu-Chi Chiang

IPC: H01L29/43 ,  H01L27/06 ,  H01L49/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/49 ,  H01L29/78 ,  H01L29/66 ,  H01L27/08

Abstract: A semiconductor structure can include a resistor on a substrate formed simultaneously with other devices, such as transistors. A diffusion barrier layer formed on a substrate is patterned to form a resistor and barrier layers under a transistor gate. A filler material, a first connector, and a second connector are formed on the resistor at the same manner and time as the gate of the transistor. The filler material is removed to form a resistor on a substrate.

公开(公告)号：US20240429281A1

公开(公告)日：2024-12-26

申请号：US18339596

申请日：2023-06-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Sheng Chen ,  Ju-Li Huang ,  Shu-Hui Wang ,  Jeng-Ya Yeh

IPC: H01L29/06 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A method of manufacturing a semiconductor device includes forming a first stack of nanostructures suspended in a first region, a second stack of nanostructures suspended in a second region, and a third stack of nanostructures suspended in a third region, depositing a first work function (WF) layer wrapping around the nanostructures in the first, second, and third regions, removing the first WF layer from the first and second regions, depositing a second WF layer wrapping around the nanostructures in the first and second regions and over the first WF layer in the third region, removing the second WF layer from the first region, depositing a third WF layer wrapping around the nanostructures in the first region and over the second WF layer in the second and third regions, and forming a capping layer over the third WF layer in the first, second, and third regions.

公开(公告)号：US20240047273A1

公开(公告)日：2024-02-08

申请号：US17881430

申请日：2022-08-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsin-Che Chiang ,  Jyun-Hong Huang ,  Chi-Wei Wu ,  Shu-Hui Wang ,  Jeng-Ya Yeh

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/762

CPC classification number: H01L21/823481 ,  H01L27/0886 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437

Abstract: Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes receiving a workpiece including a first semiconductor fin and a second semiconductor fin penetrating from a substrate and separated by a first isolation feature, and a gate structure intersecting the first semiconductor fin and the second semiconductor fin. The method also includes removing the gate structure and portions of the first semiconductor fin, the second semiconductor fin, and the first isolation feature disposed directly under the gate structure to form a fin isolation trench, forming a dielectric layer over the workpiece to substantially fill the fin isolation trench, and planarizing the dielectric layer to form a fin isolation structure in the fin isolation trench.

公开(公告)号：US20170062578A1

公开(公告)日：2017-03-02

申请号：US15351139

申请日：2016-11-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hua Feng Chen ,  Shu-Hui Wang ,  Mu-Chi Chiang

IPC: H01L29/43 ,  H01L29/49 ,  H01L29/06 ,  H01L27/06 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/78 ,  H01L49/02 ,  H01L29/08

CPC classification number: H01L29/435 ,  H01L27/0629 ,  H01L27/0802 ,  H01L28/20 ,  H01L28/24 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/4941 ,  H01L29/66545 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure can include a resistor on a substrate formed simultaneously with other devices, such as transistors. A diffusion barrier layer formed on a substrate is patterned to form a resistor and barrier layers under a transistor gate. A filler material, a first connector, and a second connector are formed on the resistor at the same manner and time as the gate of the transistor. The filler material is removed to form a resistor on a substrate.

Abstract translation: 半导体结构可以包括与诸如晶体管的其它器件同时形成的衬底上的电阻器。 形成在基板上的扩散阻挡层被图案化以在晶体管栅极下形成电阻器和势垒层。 以与晶体管的栅极相同的方式和时间，在电阻器上形成填充材料，第一连接器和第二连接器。 去除填充材料以在基底上形成电阻器。