公开(公告)号：US09570561B2

公开(公告)日：2017-02-14

申请号：US14179601

申请日：2014-02-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ru-Shang Hsiao ,  Yi-Ju Chen ,  Sheng-Fu Yu ,  I-Shan Huang ,  Kuan Yu Chen ,  Li-Yi Chen

IPC分类号： H01L29/36 ,  H01L29/78 ,  H01L27/088 ,  H01L29/66 ,  H01L21/265

CPC分类号： H01L29/36 ,  H01L21/26586 ,  H01L27/0886 ,  H01L29/1041 ,  H01L29/66803 ,  H01L29/7854 ,  H01L2029/7858

摘要： Some embodiments relate to an integrated circuit (IC) including one or more finFET devices. A finFET includes a fin of semiconductor material extending upwards from a semiconductor substrate. First and second source/drain regions, which have a first doping type, are spaced apart laterally from one another in the fin. A channel region is disposed in the fin and physically separates the first and second source/drain regions from one another. The channel region has a second doping type opposite the first doping type. A conductive gate electrode straddles the fin about the channel region and is separated from the channel region by a gate dielectric. A shallow doped region, which has the first doping type, is disposed near a surface of the fin around upper and sidewall fin regions. The shallow doped region extends continuously under the gate electrode between outer edges of the gate electrode.

摘要翻译： 一些实施例涉及包括一个或多个finFET器件的集成电路（IC）。 finFET包括从半导体衬底向上延伸的半导体材料的鳍。 具有第一掺杂类型的第一和第二源极/漏极区域在翅片中彼此间隔开。 沟道区域设置在翅片中并且将第一和第二源极/漏极区彼此物理分离。 沟道区具有与第一掺杂类型相反的第二掺杂型。 导电栅极电极跨过沟道区域的鳍状物并且通过栅极电介质与沟道区域分离。 具有第一掺杂类型的浅掺杂区域设置在翅片周围的上侧壁和侧壁翅片区域附近。 浅掺杂区域在栅电极的外边缘之间的栅电极下连续延伸。

公开(公告)号：US20160035726A1

公开(公告)日：2016-02-04

申请号：US14880454

申请日：2015-10-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ru-Shang Hsiao ,  Chien-Hsun Lin ,  Sheng-Fu Yu ,  Yu-Chang Liang ,  Kuan Yu Chen ,  Li-Yi Chen

IPC分类号： H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/04

CPC分类号： H01L27/0886 ,  H01L29/04 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/7853 ,  H01L29/7854

摘要： A FinFET device includes a dielectric layer formed over a semiconductor substrate and having an upper dielectric layer surface. A fin of semiconductor material extends upwards from the substrate through an opening in the dielectric layer. A base portion of the fin, which is recessed below the upper dielectric layer surface, includes a base channel region that separates first and second base source/drain regions. An upper channel region extends upwards from the base channel region and terminates in an upper fin surface disposed above the upper dielectric layer surface. A gate electrode straddles the upper channel region and is separated from the upper channel region by a gate dielectric. First and second epitaxial source/drain regions meet the first and second base source/drain regions, respectively, at first and second interfaces, respectively. The first and second interfaces are recessed in the opening and arranged below the upper dielectric layer surface.

公开(公告)号：US20150279975A1

公开(公告)日：2015-10-01

申请号：US14225912

申请日：2014-03-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ru-Shang Hsiao ,  Chien-Hsun Lin ,  Sheng-Fu Yu ,  Yu-Chang Liang ,  Kuan Yu Chen ,  Li-Yi Chen

IPC分类号： H01L29/66 ,  H01L29/10 ,  H01L27/088

CPC分类号： H01L27/0886 ,  H01L29/04 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/7853 ,  H01L29/7854

摘要： A FinFET device includes a dielectric layer formed over a semiconductor substrate and having an upper dielectric layer surface. A fin of semiconductor material extends upwards from the substrate through an opening in the dielectric layer. A base portion of the fin, which is recessed below the upper dielectric layer surface, includes a base channel region that separates first and second base source/drain regions. An upper channel region extends upwards from the base channel region and terminates in an upper fin surface disposed above the upper dielectric layer surface. A gate electrode straddles the upper channel region and is separated from the upper channel region by a gate dielectric. First and second epitaxial source/drain regions meet the first and second base source/drain regions, respectively, at first and second interfaces, respectively. The first and second interfaces are recessed in the opening and arranged below the upper dielectric layer surface.

摘要翻译： FinFET器件包括形成在半导体衬底上并具有上电介质层表面的电介质层。 半导体材料的翅片从基板向上延伸穿过电介质层中的开口。 鳍状物的底部凹陷在上介电层表面下方，包括分隔第一和第二基极/漏极区的基极沟道区。 上通道区域从基通道区域向上延伸并且终止于设置在上电介质层表面上方的上散热片表面。 栅电极跨越上沟道区，并通过栅极电介质与上沟道区分离。 第一和第二外延源极/漏极区分别在第一和第二界面处分别与第一和第二基极源极/漏极区域相交。 第一和第二接口凹入开口并且布置在上电介质层表面的下方。

公开(公告)号：US20240282671A1

公开(公告)日：2024-08-22

申请号：US18327998

申请日：2023-06-02

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuan Yu Chen ,  Chun-Yen Lin ,  Hsin Yang Hung ,  Ching-Yu Huang ,  Wei-Cheng Lin ,  Jiann-Tyng Tzeng ,  Ting-Yun Wu ,  Wei-De Ho ,  Szuya Liao

IPC分类号： H01L23/48 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/417 ,  H01L29/66

CPC分类号： H01L23/481 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/41733 ,  H01L29/66545

摘要： A method includes forming a multi-layer stack comprising dummy layers and semiconductor layers located alternatingly, and forming a plurality of dummy gate stacks on sidewalls and a top surface of the multi-layer stack. Two of the plurality of dummy gate stacks are immediately neighboring each other, and have a space in between. A first source/drain region and a second source/drain region are formed in the multi-layer stack, with the second source/drain region overlapping the first source/drain region. The method further includes replacing the plurality of dummy gate stacks with a plurality of replacement gate stacks, replacing a first one of the plurality of replacement gate stacks with a first dielectric isolation region, forming a deep contact plug in the space, forming a front-side via over the deep contact plug, and forming a back-side via under the deep contact plug, wherein the front-side via is electrically connected to the back-side via through the deep contact plug.

公开(公告)号：US20150228731A1

公开(公告)日：2015-08-13

申请号：US14179601

申请日：2014-02-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ru-Shang Hsiao ,  Yi-Ju Chen ,  Sheng-Fu Yu ,  I-Shan Huang ,  Kuan Yu Chen ,  Li-Yi Chen

IPC分类号： H01L29/36 ,  H01L21/265 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088

CPC分类号： H01L29/36 ,  H01L21/26586 ,  H01L27/0886 ,  H01L29/1041 ,  H01L29/66803 ,  H01L29/7854 ,  H01L2029/7858

摘要： Some embodiments relate to an integrated circuit (IC) including one or more finFET devices. A finFET includes a fin of semiconductor material extending upwards from a semiconductor substrate. First and second source/drain regions, which have a first doping type, are spaced apart laterally from one another in the fin. A channel region is disposed in the fin and physically separates the first and second source/drain regions from one another. The channel region has a second doping type opposite the first doping type. A conductive gate electrode straddles the fin about the channel region and is separated from the channel region by a gate dielectric. A shallow doped region, which has the first doping type, is disposed near a surface of the fin around upper and sidewall fin regions. The shallow doped region extends continuously under the gate electrode between outer edges of the gate electrode.

摘要翻译： 一些实施例涉及包括一个或多个finFET器件的集成电路（IC）。 finFET包括从半导体衬底向上延伸的半导体材料的鳍。 具有第一掺杂类型的第一和第二源极/漏极区域在翅片中彼此间隔开。 沟道区域设置在翅片中并且将第一和第二源极/漏极区彼此物理分离。 沟道区具有与第一掺杂类型相反的第二掺杂型。 导电栅极电极跨过沟道区域的鳍状物并且通过栅极电介质与沟道区域分离。 具有第一掺杂类型的浅掺杂区域设置在翅片周围的上侧壁和侧壁翅片区域附近。 浅掺杂区域在栅电极的外边缘之间的栅电极下连续延伸。

公开(公告)号：US09490254B2

公开(公告)日：2016-11-08

申请号：US14880454

申请日：2015-10-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ru-Shang Hsiao ,  Chien-Hsun Lin ,  Sheng-Fu Yu ,  Yu-Chang Liang ,  Kuan Yu Chen ,  Li-Yi Chen

IPC分类号： H01L29/76 ,  H01L21/84 ,  H01L27/088 ,  H01L29/66 ,  H01L29/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L27/0886 ,  H01L29/04 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/7853 ,  H01L29/7854

摘要： A FinFET device includes a dielectric layer formed over a semiconductor substrate and having an upper dielectric layer surface. A fin of semiconductor material extends upwards from the substrate through an opening in the dielectric layer. A base portion of the fin, which is recessed below the upper dielectric layer surface, includes a base channel region that separates first and second base source/drain regions. An upper channel region extends upwards from the base channel region and terminates in an upper fin surface disposed above the upper dielectric layer surface. A gate electrode straddles the upper channel region and is separated from the upper channel region by a gate dielectric. First and second epitaxial source/drain regions meet the first and second base source/drain regions, respectively, at first and second interfaces, respectively. The first and second interfaces are recessed in the opening and arranged below the upper dielectric layer surface.

公开(公告)号：US09159812B1

公开(公告)日：2015-10-13

申请号：US14225912

申请日：2014-03-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ru-Shang Hsiao ,  Chien-Hsun Lin ,  Sheng-Fu Yu ,  Yu-Chang Liang ,  Kuan Yu Chen ,  Li-Yi Chen

IPC分类号： H01L21/84 ,  H01L29/76 ,  H01L29/66 ,  H01L27/088 ,  H01L29/10

CPC分类号： H01L27/0886 ,  H01L29/04 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/7853 ,  H01L29/7854

摘要： A FinFET device includes a dielectric layer formed over a semiconductor substrate and having an upper dielectric layer surface. A fin of semiconductor material extends upwards from the substrate through an opening in the dielectric layer. A base portion of the fin, which is recessed below the upper dielectric layer surface, includes a base channel region that separates first and second base source/drain regions. An upper channel region extends upwards from the base channel region and terminates in an upper fin surface disposed above the upper dielectric layer surface. A gate electrode straddles the upper channel region and is separated from the upper channel region by a gate dielectric. First and second epitaxial source/drain regions meet the first and second base source/drain regions, respectively, at first and second interfaces, respectively. The first and second interfaces are recessed in the opening and arranged below the upper dielectric layer surface.

摘要翻译： FinFET器件包括形成在半导体衬底上并具有上电介质层表面的电介质层。 半导体材料的翅片从基板向上延伸穿过电介质层中的开口。 鳍状物的底部凹陷在上介电层表面下方，包括分隔第一和第二基极/漏极区的基极沟道区。 上通道区域从基通道区域向上延伸并且终止于设置在上电介质层表面上方的上散热片表面。 栅电极跨越上沟道区，并通过栅极电介质与上沟道区分离。 第一和第二外延源极/漏极区分别在第一和第二界面处分别与第一和第二基极源极/漏极区域相交。 第一和第二接口凹入开口并且布置在上电介质层表面的下方。