公开(公告)号：US20230147413A1

公开(公告)日：2023-05-11

申请号：US18149265

申请日：2023-01-03

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Kuo-Chiang Tsai ,  Yi-Ju Chen ,  Jyh-Huei Chen

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/02

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5226 ,  H01L27/0207 ,  H01L21/76897 ,  H01L21/823418 ,  H01L29/0847

Abstract: A semiconductor device includes a source feature and a drain feature disposed over a substrate. The semiconductor device includes a source via electrically coupled to the source feature and a drain via electrically coupled to the drain feature. The semiconductor device includes a source via metal line disposed over and directly connected to the source via. The semiconductor device includes and a drain via metal line disposed over and directly connected to the drain via. The source via metal line has two first outer edges extending lengthwise along a first direction and at least one of the first outer edges is substantially aligned with an edge of the source via from a top view. The drain via metal line has two second outer edges extending lengthwise along the first direction and the two second outer edges are offset from edges of the drain via from a top view.

公开(公告)号：US20150228731A1

公开(公告)日：2015-08-13

申请号：US14179601

申请日：2014-02-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Yi-Ju Chen ,  Sheng-Fu Yu ,  I-Shan Huang ,  Kuan Yu Chen ,  Li-Yi Chen

IPC: H01L29/36 ,  H01L21/265 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L29/36 ,  H01L21/26586 ,  H01L27/0886 ,  H01L29/1041 ,  H01L29/66803 ,  H01L29/7854 ,  H01L2029/7858

Abstract: Some embodiments relate to an integrated circuit (IC) including one or more finFET devices. A finFET includes a fin of semiconductor material extending upwards from a semiconductor substrate. First and second source/drain regions, which have a first doping type, are spaced apart laterally from one another in the fin. A channel region is disposed in the fin and physically separates the first and second source/drain regions from one another. The channel region has a second doping type opposite the first doping type. A conductive gate electrode straddles the fin about the channel region and is separated from the channel region by a gate dielectric. A shallow doped region, which has the first doping type, is disposed near a surface of the fin around upper and sidewall fin regions. The shallow doped region extends continuously under the gate electrode between outer edges of the gate electrode.

Abstract translation: 一些实施例涉及包括一个或多个finFET器件的集成电路（IC）。 finFET包括从半导体衬底向上延伸的半导体材料的鳍。 具有第一掺杂类型的第一和第二源极/漏极区域在翅片中彼此间隔开。 沟道区域设置在翅片中并且将第一和第二源极/漏极区彼此物理分离。 沟道区具有与第一掺杂类型相反的第二掺杂型。 导电栅极电极跨过沟道区域的鳍状物并且通过栅极电介质与沟道区域分离。 具有第一掺杂类型的浅掺杂区域设置在翅片周围的上侧壁和侧壁翅片区域附近。 浅掺杂区域在栅电极的外边缘之间的栅电极下连续延伸。

公开(公告)号：US11139203B2

公开(公告)日：2021-10-05

申请号：US16263143

申请日：2019-01-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Tsai ,  Ke-Jing Yu ,  Fu-Hsiang Su ,  Yi-Ju Chen ,  Jyh-Huei Chen

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/08 ,  H01L21/308 ,  H01L21/311

Abstract: A source/drain region is disposed in a substrate. A gate structure is disposed over the substrate. A gate spacer is disposed on a sidewall of the gate structure. The gate spacer and the gate structure have substantially similar heights. A via is disposed over and electrically coupled to: the source/drain region or the gate structure. A mask layer is disposed over the gate spacer. The mask layer has a greater dielectric constant than the gate spacer. A first side of the mask layer is disposed adjacent to the via. A dielectric layer is disposed on a second side of the mask layer, wherein the mask layer is disposed between the dielectric layer and the via.

公开(公告)号：US10666438B2

公开(公告)日：2020-05-26

申请号：US16160397

申请日：2018-10-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Che Tsai ,  Cheng Hung Lee ,  Shih-Lien Linus Lu ,  Yi-Ju Chen

IPC: H04L9/32 ,  G11C7/08 ,  G11C7/12 ,  G06F21/73

Abstract: A memory storage device is fabricated using a semiconductor fabrication process. Often times, manufacturing variations and/or misalignment tolerances present within the semiconductor fabrication process can cause the memory storage device to differ from other memory storage devices similarly designed and fabricated by the semiconductor fabrication process. For example, uncontrollable random physical processes in the semiconductor fabrication process can cause small differences, such as differences in doping concentrations, oxide thicknesses, channel lengths, structural widths, and/or parasitics to provide some examples, between these memory storage devices. These small differences can cause bitlines within the memory storage device to be physically unique with no two bitlines being identical. As a result, the uncontrollable random physical processes in the semiconductor fabrication process can cause electronic data read from the memory storage device to propagate along the bitlines at different rates. This physical uniqueness of the bitlines can be utilized to implement a physical unclonable function (PUF) allowing the memory storage device to be differentiated from other memory storage devices similarly designed and fabricated by the semiconductor fabrication process.

公开(公告)号：US09570561B2

公开(公告)日：2017-02-14

申请号：US14179601

申请日：2014-02-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Yi-Ju Chen ,  Sheng-Fu Yu ,  I-Shan Huang ,  Kuan Yu Chen ,  Li-Yi Chen

IPC: H01L29/36 ,  H01L29/78 ,  H01L27/088 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/36 ,  H01L21/26586 ,  H01L27/0886 ,  H01L29/1041 ,  H01L29/66803 ,  H01L29/7854 ,  H01L2029/7858

Abstract: Some embodiments relate to an integrated circuit (IC) including one or more finFET devices. A finFET includes a fin of semiconductor material extending upwards from a semiconductor substrate. First and second source/drain regions, which have a first doping type, are spaced apart laterally from one another in the fin. A channel region is disposed in the fin and physically separates the first and second source/drain regions from one another. The channel region has a second doping type opposite the first doping type. A conductive gate electrode straddles the fin about the channel region and is separated from the channel region by a gate dielectric. A shallow doped region, which has the first doping type, is disposed near a surface of the fin around upper and sidewall fin regions. The shallow doped region extends continuously under the gate electrode between outer edges of the gate electrode.

Abstract translation: 一些实施例涉及包括一个或多个finFET器件的集成电路（IC）。 finFET包括从半导体衬底向上延伸的半导体材料的鳍。 具有第一掺杂类型的第一和第二源极/漏极区域在翅片中彼此间隔开。 沟道区域设置在翅片中并且将第一和第二源极/漏极区彼此物理分离。 沟道区具有与第一掺杂类型相反的第二掺杂型。 导电栅极电极跨过沟道区域的鳍状物并且通过栅极电介质与沟道区域分离。 具有第一掺杂类型的浅掺杂区域设置在翅片周围的上侧壁和侧壁翅片区域附近。 浅掺杂区域在栅电极的外边缘之间的栅电极下连续延伸。

公开(公告)号：US11545432B2

公开(公告)日：2023-01-03

申请号：US17083976

申请日：2020-10-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Tsai ,  Yi-Ju Chen ,  Jyh-Huei Chen

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/02 ,  H01L29/417 ,  H01L29/08 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/768

Abstract: An exemplary semiconductor device includes a source feature and a drain feature disposed over a substrate. The semiconductor device further includes a source via electrically coupled to the source feature, and a drain via electrically coupled to the drain feature. The source via has a first size; the drain via has a second size; and the first size is greater than the second size. The semiconductor device may further include a first metal line electrically coupled to the source via and a second metal line electrically coupled to the drain via. The source via has a first dimension matching a dimension of the first metal line, and the drain via has a second dimension matching a dimension of the second metal line. The first metal line may be wider than the second metal line.

公开(公告)号：US20220359393A1

公开(公告)日：2022-11-10

申请号：US17873782

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Tsai ,  Yi-Ju Chen ,  Jyh-Huei Chen

IPC: H01L23/528 ,  H01L21/8234 ,  H01L23/522 ,  H01L21/768 ,  H01L27/02

Abstract: A method includes receiving a semiconductor structure having a source contact feature electrically connected to a source feature and a drain contact feature electrically connected to a drain feature. The method includes etching to form a drain via trench over the drain contact feature and forming a drain via in the drain via trench. After forming the drain via, the method further includes etching to form a source via trench over the source contact feature and forming a source via in the source via trench. The drain via has a first dimension along a first direction, the source via has a second dimension along the first direction, and the second dimension is greater than the first dimension.

公开(公告)号：US20210272901A1

公开(公告)日：2021-09-02

申请号：US17083976

申请日：2020-10-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Tsai ,  Yi-Ju Chen ,  Jyh-Huei Chen

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/8234

Abstract: An exemplary semiconductor device includes a source feature and a drain feature disposed over a substrate. The semiconductor device further includes a source via electrically coupled to the source feature, and a drain via electrically coupled to the drain feature. The source via has a first size; the drain via has a second size; and the first size is greater than the second size. The semiconductor device may further include a first metal line electrically coupled to the source via and a second metal line electrically coupled to the drain via. The source via has a first dimension matching a dimension of the first metal line, and the drain via has a second dimension matching a dimension of the second metal line. The first metal line may be wider than the second metal line.

公开(公告)号：US12154856B2

公开(公告)日：2024-11-26

申请号：US17873782

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Tsai ,  Yi-Ju Chen ,  Jyh-Huei Chen

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78

Abstract: A method includes receiving a semiconductor structure having a source contact feature electrically connected to a source feature and a drain contact feature electrically connected to a drain feature. The method includes etching to form a drain via trench over the drain contact feature and forming a drain via in the drain via trench. After forming the drain via, the method further includes etching to form a source via trench over the source contact feature and forming a source via in the source via trench. The drain via has a first dimension along a first direction, the source via has a second dimension along the first direction, and the second dimension is greater than the first dimension.

公开(公告)号：US10950729B2

公开(公告)日：2021-03-16

申请号：US16171763

申请日：2018-10-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Tsai ,  Fu-Hsiang Su ,  Yi-Ju Chen ,  Jyh-Huei Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/02 ,  H01L23/522

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack formed over a semiconductor substrate, a source/drain contact structure adjacent to the gate stack, and a gate spacer formed between the gate stack and the source/drain contact structure. The semiconductor device structure also includes a first insulating capping feature covering an upper surface of the gate stack, a second insulating capping feature covering an upper surface of the source/drain contact structure, and an insulating layer covering the upper surfaces of the first insulating capping feature and the second insulating capping feature. The second insulating capping feature includes a material that is different from a material of the first insulating capping feature. The semiconductor device structure also includes a via structure passing through the insulating layer and the first insulating capping feature and electrically connected to the gate stack.