公开(公告)号：US20230147413A1

公开(公告)日：2023-05-11

申请号：US18149265

申请日：2023-01-03

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Kuo-Chiang Tsai ,  Yi-Ju Chen ,  Jyh-Huei Chen

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/02

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5226 ,  H01L27/0207 ,  H01L21/76897 ,  H01L21/823418 ,  H01L29/0847

Abstract: A semiconductor device includes a source feature and a drain feature disposed over a substrate. The semiconductor device includes a source via electrically coupled to the source feature and a drain via electrically coupled to the drain feature. The semiconductor device includes a source via metal line disposed over and directly connected to the source via. The semiconductor device includes and a drain via metal line disposed over and directly connected to the drain via. The source via metal line has two first outer edges extending lengthwise along a first direction and at least one of the first outer edges is substantially aligned with an edge of the source via from a top view. The drain via metal line has two second outer edges extending lengthwise along the first direction and the two second outer edges are offset from edges of the drain via from a top view.

公开(公告)号：US11239114B2

公开(公告)日：2022-02-01

申请号：US16571358

申请日：2019-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Tsai ,  Jhy-Huei Chen

IPC: H01L21/768 ,  H01L23/522 ,  H01L29/66 ,  H01L29/78

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate; a gate structure disposed over the substrate and over a channel region of the semiconductor device, wherein the gate structure includes a gate stack and spacers disposed along sidewalls of the gate stack, the gate stack including a gate dielectric layer and a gate electrode; a first metal layer disposed over the gate stack, wherein the first metal layer laterally contacts the spacers over the gate dielectric layer and the gate electrode; and a gate via disposed over the first metal layer.

公开(公告)号：US11081585B2

公开(公告)日：2021-08-03

申请号：US16907781

申请日：2020-06-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Tsai ,  Fu-Hsiang Su ,  Ke-Jing Yu ,  Chih-Hong Hwang ,  Jyh-Huei Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L21/48 ,  H01L21/768 ,  H01L23/522

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an insulating layer over a substrate, a gate stack formed in the insulating layer, and an insulating capping layer formed in the insulating layer to cover the gate stack. The semiconductor device structure also includes a source/drain contact structure adjacent to the gate stack. The source/drain contact structure has a sidewall that is in direct contact with a sidewall of the insulating capping layer, and an upper surface that is substantially level with an upper surface of the insulating capping layer and an upper surface of the insulating layer. In addition, the semiconductor device structure includes a first via structure above and electrically connected to the gate stack and a second via structure above and electrically connected to the source/drain contact structure.

公开(公告)号：US10950497B2

公开(公告)日：2021-03-16

申请号：US16371780

申请日：2019-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Tsai ,  Jyh-Huei Chen

IPC: H01L21/00 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/311 ,  H01L23/522 ,  H01L21/321 ,  H01L21/027

Abstract: In one example, a method includes performing a first etching process to pattern a dielectric layer and expose a contact etch stop layer, performing a second etching process to remove the etch stop layer and expose a top surface of an underlying feature, performing a third etching process to laterally recess the etch stop layer, and depositing a conductive material over the underlying feature to create a conductive feature in direct contact with the underlying feature.

公开(公告)号：US10658237B2

公开(公告)日：2020-05-19

申请号：US16175802

申请日：2018-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Hsiang Su ,  Jyh-Huei Chen ,  Kuo-Chiang Tsai ,  Ke-Jing Yu

IPC: H01L29/06 ,  H01L21/768 ,  H01L27/092 ,  H01L23/535 ,  H01L21/033 ,  H01L21/8238

Abstract: Semiconductor devices are provided, and includes a substrate, a first gate structure and a second gate structure over the substrate, a first hard mask on the first gate structure and a second hard mask on the second gate structure and a third hard mask. The third hard mask is disposed in a dielectric layer between the first gate structure and the second gate structure and disposed between the first hard mask and the second hard mask.

公开(公告)号：US20240387665A1

公开(公告)日：2024-11-21

申请号：US18789227

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Tsai ,  Jyh-Huei Chen

IPC: H01L29/417 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/088 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: FinFET devices with source/drain contacts with reduced resistance/capacitance power loss and with an enhanced processing window between the source/drain contacts and a gate via and methods of manufacture are described herein. A metal riser may be formed in a first recess of a source/drain contact of a first material. The metal riser and a contact via may be formed from a second material and the contact via may be formed over the metal riser to provide a hybrid source/drain contact of a finFET with a wide surface contact area at an interface between the source/drain contact and the metal riser. A dielectric fill material and/or a conformal contact etch stop layer may be used to form an isolation region in a second recess of the source/drain contact to extend a processing window disposed between the isolation region and a gate contact of the finFET.

公开(公告)号：US12107133B2

公开(公告)日：2024-10-01

申请号：US17379265

申请日：2021-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Tsai ,  Jyh-Huei Chen

IPC: H01L29/417 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/088 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/66795 ,  H01L29/7851

Abstract: FinFET devices with source/drain contacts with reduced resistance/capacitance power loss and with an enhanced processing window between the source/drain contacts and a gate via and methods of manufacture are described herein. A metal riser may be formed in a first recess of a source/drain contact of a first material. The metal riser and a contact via may be formed from a second material and the contact via may be formed over the metal riser to provide a hybrid source/drain contact of a finFET with a wide surface contact area at an interface between the source/drain contact and the metal riser. A dielectric fill material and/or a conformal contact etch stop layer may be used to form an isolation region in a second recess of the source/drain contact to extend a processing window disposed between the isolation region and a gate contact of the finFET.

公开(公告)号：US20210202309A1

公开(公告)日：2021-07-01

申请号：US17201637

申请日：2021-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Tsai ,  Jyh-Huei Chen

IPC: H01L21/768 ,  H01L21/3213 ,  H01L21/311 ,  H01L23/522

Abstract: In one example, a method includes performing a first etching process to pattern a dielectric layer and expose a contact etch stop layer, performing a second etching process to remove the etch stop layer and expose a top surface of an underlying feature, performing a third etching process to laterally recess the etch stop layer, and depositing a conductive material over the underlying feature to create a conductive feature in direct contact with the underlying feature.

公开(公告)号：US10693004B2

公开(公告)日：2020-06-23

申请号：US16163970

申请日：2018-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Tsai ,  Fu-Hsiang Su ,  Ke-Jing Yu ,  Chih-Hong Hwang ,  Jyh-Huei Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L21/48 ,  H01L21/768 ,  H01L23/522

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack over a substrate and an insulating capping layer over the gate stack. The semiconductor device structure also includes a source/drain contact structure adjacent to the gate stack and having an upper surface that is substantially level with the upper surface of the insulating capping layer. The semiconductor device structure also includes a first via structure passing through the insulating capping layer and electrically connected to the gate stack, and a second via structure above and electrically connected to the source/drain contact structure. The first via structure and the second via structure have different vertical heights.

公开(公告)号：US10665506B2

公开(公告)日：2020-05-26

申请号：US16148071

申请日：2018-10-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Wei Tseng ,  Kuo-Chiang Tsai

IPC: H01L21/768 ,  H01L23/522 ,  H01L27/11 ,  H01L21/311

Abstract: First and second gates and first and second conductive contacts are disposed over a substrate. First and second vias are disposed over the first and second conductive contacts, respectively. A first gate contact is disposed over the first gate. A dielectric structure is disposed over the first gate and over the second gate. A first portion of the dielectric structure is disposed between the first and second vias. A second portion of the dielectric structure is disposed between the first via and the first gate contact. A first interface between the first conductive contact and the first via constitutes a first percentage of an upper surface area of the first conductive contact. A second interface between the first gate and the first gate contact constitutes a second percentage of an upper surface area of the first gate. The first percentage is greater than the second percentage.