Semiconductor device with reduced via bridging risk

    公开(公告)号:US11222821B2

    公开(公告)日:2022-01-11

    申请号:US16881406

    申请日:2020-05-22

    Abstract: First and second gates and first and second conductive contacts are disposed over a substrate. First and second vias are disposed over the first and second conductive contacts, respectively. A first gate contact is disposed over the first gate. A dielectric structure is disposed over the first gate and over the second gate. A first portion of the dielectric structure is disposed between the first and second vias. A second portion of the dielectric structure is disposed between the first via and the first gate contact. A first interface between the first conductive contact and the first via constitutes a first percentage of an upper surface area of the first conductive contact. A second interface between the first gate and the first gate contact constitutes a second percentage of an upper surface area of the first gate. The first percentage is greater than the second percentage.

    Semiconductor Device With Reduced Via Bridging Risk

    公开(公告)号:US20200286783A1

    公开(公告)日:2020-09-10

    申请号:US16881406

    申请日:2020-05-22

    Abstract: First and second gates and first and second conductive contacts are disposed over a substrate. First and second vias are disposed over the first and second conductive contacts, respectively. A first gate contact is disposed over the first gate. A dielectric structure is disposed over the first gate and over the second gate. A first portion of the dielectric structure is disposed between the first and second vias. A second portion of the dielectric structure is disposed between the first via and the first gate contact. A first interface between the first conductive contact and the first via constitutes a first percentage of an upper surface area of the first conductive contact. A second interface between the first gate and the first gate contact constitutes a second percentage of an upper surface area of the first gate. The first percentage is greater than the second percentage.

    Semiconductor device with reduced via bridging risk

    公开(公告)号:US10665506B2

    公开(公告)日:2020-05-26

    申请号:US16148071

    申请日:2018-10-01

    Abstract: First and second gates and first and second conductive contacts are disposed over a substrate. First and second vias are disposed over the first and second conductive contacts, respectively. A first gate contact is disposed over the first gate. A dielectric structure is disposed over the first gate and over the second gate. A first portion of the dielectric structure is disposed between the first and second vias. A second portion of the dielectric structure is disposed between the first via and the first gate contact. A first interface between the first conductive contact and the first via constitutes a first percentage of an upper surface area of the first conductive contact. A second interface between the first gate and the first gate contact constitutes a second percentage of an upper surface area of the first gate. The first percentage is greater than the second percentage.

    SEMICONDUCTOR DEVICE WITH REDUCED VIA BRIDGING RISK

    公开(公告)号:US20200006139A1

    公开(公告)日:2020-01-02

    申请号:US16148071

    申请日:2018-10-01

    Abstract: First and second gates and first and second conductive contacts are disposed over a substrate. First and second vias are disposed over the first and second conductive contacts, respectively. A first gate contact is disposed over the first gate. A dielectric structure is disposed over the first gate and over the second gate. A first portion of the dielectric structure is disposed between the first and second vias. A second portion of the dielectric structure is disposed between the first via and the first gate contact. A first interface between the first conductive contact and the first via constitutes a first percentage of an upper surface area of the first conductive contact. A second interface between the first gate and the first gate contact constitutes a second percentage of an upper surface area of the first gate. The first percentage is greater than the second percentage.

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