公开(公告)号：US09805913B2

公开(公告)日：2017-10-31

申请号：US14727957

申请日：2015-06-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Hong Hwang ,  Chun-Lin Chang ,  Nai-Han Cheng ,  Chi-Ming Yang ,  Chin-Hsiang Lin

IPC: H01J37/317 ,  H01L21/687 ,  H01L21/265 ,  H01J37/302 ,  H01J37/147 ,  H01J37/20

CPC classification number: H01J37/3171 ,  H01J37/1474 ,  H01J37/20 ,  H01J37/3023 ,  H01J37/3172 ,  H01J2237/12 ,  H01J2237/20228 ,  H01J2237/30477 ,  H01J2237/30483 ,  H01L21/265 ,  H01L21/68764

Abstract: A process control method is provided for ion implantation methods and apparatuses, to produce a high dosage area on a substrate such as may compensate for noted non-uniformities. In an ion implantation tool, separately controllable electrodes are provided as multiple sets of opposed electrodes disposed outside an ion beam. Beam blockers are positionable into the ion beam. Both the electrodes and beam blockers are controllable to reduce the area of the ion beam that is incident upon a substrate. The electrodes and beam blockers also change the position of the reduced-area ion beam incident upon the surface. The speed at which the substrate scans past the ion beam may be dynamically changed during the implantation process to produce various dosage concentrations in the substrate.

公开(公告)号：US11081585B2

公开(公告)日：2021-08-03

申请号：US16907781

申请日：2020-06-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Tsai ,  Fu-Hsiang Su ,  Ke-Jing Yu ,  Chih-Hong Hwang ,  Jyh-Huei Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L21/48 ,  H01L21/768 ,  H01L23/522

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an insulating layer over a substrate, a gate stack formed in the insulating layer, and an insulating capping layer formed in the insulating layer to cover the gate stack. The semiconductor device structure also includes a source/drain contact structure adjacent to the gate stack. The source/drain contact structure has a sidewall that is in direct contact with a sidewall of the insulating capping layer, and an upper surface that is substantially level with an upper surface of the insulating capping layer and an upper surface of the insulating layer. In addition, the semiconductor device structure includes a first via structure above and electrically connected to the gate stack and a second via structure above and electrically connected to the source/drain contact structure.

公开(公告)号：US10693004B2

公开(公告)日：2020-06-23

申请号：US16163970

申请日：2018-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Tsai ,  Fu-Hsiang Su ,  Ke-Jing Yu ,  Chih-Hong Hwang ,  Jyh-Huei Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L21/48 ,  H01L21/768 ,  H01L23/522

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack over a substrate and an insulating capping layer over the gate stack. The semiconductor device structure also includes a source/drain contact structure adjacent to the gate stack and having an upper surface that is substantially level with the upper surface of the insulating capping layer. The semiconductor device structure also includes a first via structure passing through the insulating capping layer and electrically connected to the gate stack, and a second via structure above and electrically connected to the source/drain contact structure. The first via structure and the second via structure have different vertical heights.