公开(公告)号：US10693004B2

公开(公告)日：2020-06-23

申请号：US16163970

申请日：2018-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Tsai ,  Fu-Hsiang Su ,  Ke-Jing Yu ,  Chih-Hong Hwang ,  Jyh-Huei Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L21/48 ,  H01L21/768 ,  H01L23/522

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack over a substrate and an insulating capping layer over the gate stack. The semiconductor device structure also includes a source/drain contact structure adjacent to the gate stack and having an upper surface that is substantially level with the upper surface of the insulating capping layer. The semiconductor device structure also includes a first via structure passing through the insulating capping layer and electrically connected to the gate stack, and a second via structure above and electrically connected to the source/drain contact structure. The first via structure and the second via structure have different vertical heights.

公开(公告)号：US11139203B2

公开(公告)日：2021-10-05

申请号：US16263143

申请日：2019-01-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Tsai ,  Ke-Jing Yu ,  Fu-Hsiang Su ,  Yi-Ju Chen ,  Jyh-Huei Chen

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/08 ,  H01L21/308 ,  H01L21/311

Abstract: A source/drain region is disposed in a substrate. A gate structure is disposed over the substrate. A gate spacer is disposed on a sidewall of the gate structure. The gate spacer and the gate structure have substantially similar heights. A via is disposed over and electrically coupled to: the source/drain region or the gate structure. A mask layer is disposed over the gate spacer. The mask layer has a greater dielectric constant than the gate spacer. A first side of the mask layer is disposed adjacent to the via. A dielectric layer is disposed on a second side of the mask layer, wherein the mask layer is disposed between the dielectric layer and the via.

公开(公告)号：US20200279774A1

公开(公告)日：2020-09-03

申请号：US16876127

申请日：2020-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Hsiang Su ,  Jyh-Huei Chen ,  Kuo-Chiang Tsai ,  Ke-Jing Yu

IPC: H01L21/768 ,  H01L27/092 ,  H01L23/535 ,  H01L21/033 ,  H01L21/8238

Abstract: A semiconductor device includes a substrate, a first gate structure and a second gate structure over the substrate, a first hard mask on a top surface of the first gate structure, a second hard mask on the second gate structure and a third hard mask disposed between the first gate structure and the second gate structure and disposed between the first hard mask and the second hard mask. A bottom surface of the third hard mask is substantially flush with a bottom surface of the first gate structure.

公开(公告)号：US20200043787A1

公开(公告)日：2020-02-06

申请号：US16175802

申请日：2018-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Hsiang Su ,  Jyh-Huei Chen ,  Kuo-Chiang Tsai ,  Ke-Jing Yu

IPC: H01L21/768 ,  H01L27/092 ,  H01L23/535 ,  H01L21/8238 ,  H01L21/033

Abstract: Semiconductor devices are provided, and includes a substrate, a first gate structure and a second gate structure over the substrate, a first hard mask on the first gate structure and a second hard mask on the second gate structure and a third hard mask. The third hard mask is disposed in a dielectric layer between the first gate structure and the second gate structure and disposed between the first hard mask and the second hard mask.

公开(公告)号：US11081585B2

公开(公告)日：2021-08-03

申请号：US16907781

申请日：2020-06-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Tsai ,  Fu-Hsiang Su ,  Ke-Jing Yu ,  Chih-Hong Hwang ,  Jyh-Huei Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L21/48 ,  H01L21/768 ,  H01L23/522

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an insulating layer over a substrate, a gate stack formed in the insulating layer, and an insulating capping layer formed in the insulating layer to cover the gate stack. The semiconductor device structure also includes a source/drain contact structure adjacent to the gate stack. The source/drain contact structure has a sidewall that is in direct contact with a sidewall of the insulating capping layer, and an upper surface that is substantially level with an upper surface of the insulating capping layer and an upper surface of the insulating layer. In addition, the semiconductor device structure includes a first via structure above and electrically connected to the gate stack and a second via structure above and electrically connected to the source/drain contact structure.

公开(公告)号：US10658237B2

公开(公告)日：2020-05-19

申请号：US16175802

申请日：2018-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Hsiang Su ,  Jyh-Huei Chen ,  Kuo-Chiang Tsai ,  Ke-Jing Yu

IPC: H01L29/06 ,  H01L21/768 ,  H01L27/092 ,  H01L23/535 ,  H01L21/033 ,  H01L21/8238

Abstract: Semiconductor devices are provided, and includes a substrate, a first gate structure and a second gate structure over the substrate, a first hard mask on the first gate structure and a second hard mask on the second gate structure and a third hard mask. The third hard mask is disposed in a dielectric layer between the first gate structure and the second gate structure and disposed between the first hard mask and the second hard mask.

公开(公告)号：US11018057B2

公开(公告)日：2021-05-25

申请号：US16876127

申请日：2020-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Hsiang Su ,  Jyh-Huei Chen ,  Kuo-Chiang Tsai ,  Ke-Jing Yu

IPC: H01L21/768 ,  H01L27/092 ,  H01L23/535 ,  H01L21/033 ,  H01L21/8238

Abstract: A semiconductor device includes a substrate, a first gate structure and a second gate structure over the substrate, a first hard mask on a top surface of the first gate structure, a second hard mask on the second gate structure and a third hard mask disposed between the first gate structure and the second gate structure and disposed between the first hard mask and the second hard mask. A bottom surface of the third hard mask is substantially flush with a bottom surface of the first gate structure.

公开(公告)号：US10950729B2

公开(公告)日：2021-03-16

申请号：US16171763

申请日：2018-10-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Tsai ,  Fu-Hsiang Su ,  Yi-Ju Chen ,  Jyh-Huei Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/02 ,  H01L23/522

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack formed over a semiconductor substrate, a source/drain contact structure adjacent to the gate stack, and a gate spacer formed between the gate stack and the source/drain contact structure. The semiconductor device structure also includes a first insulating capping feature covering an upper surface of the gate stack, a second insulating capping feature covering an upper surface of the source/drain contact structure, and an insulating layer covering the upper surfaces of the first insulating capping feature and the second insulating capping feature. The second insulating capping feature includes a material that is different from a material of the first insulating capping feature. The semiconductor device structure also includes a via structure passing through the insulating layer and the first insulating capping feature and electrically connected to the gate stack.

公开(公告)号：US10825721B2

公开(公告)日：2020-11-03

申请号：US16180913

申请日：2018-11-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Tsai ,  Fu-Hsiang Su ,  Ke-Jing Yu ,  Jyh-Huei Chen

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/49 ,  H01L29/417 ,  H01L29/78

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack formed over a semiconductor substrate, a source/drain contact structure laterally adjacent to the gate stack, and a gate spacer formed between the gate stack and the source/drain contact structure. The semiconductor device structure also includes a first insulating capping feature covering the upper surface of the gate stack, a second insulating capping feature covering the upper surface of the source/drain contact structure, and an insulating layer covering the upper surfaces of the first insulating capping feature and the second insulating capping feature. The second insulating capping feature includes a material that is different from the material of the first insulating capping feature. The semiconductor device structure also includes a via structure passing through the insulating layer and the first insulating capping feature and electrically connected to the gate stack.