公开(公告)号：US20150228731A1

公开(公告)日：2015-08-13

申请号：US14179601

申请日：2014-02-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Yi-Ju Chen ,  Sheng-Fu Yu ,  I-Shan Huang ,  Kuan Yu Chen ,  Li-Yi Chen

IPC: H01L29/36 ,  H01L21/265 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L29/36 ,  H01L21/26586 ,  H01L27/0886 ,  H01L29/1041 ,  H01L29/66803 ,  H01L29/7854 ,  H01L2029/7858

Abstract: Some embodiments relate to an integrated circuit (IC) including one or more finFET devices. A finFET includes a fin of semiconductor material extending upwards from a semiconductor substrate. First and second source/drain regions, which have a first doping type, are spaced apart laterally from one another in the fin. A channel region is disposed in the fin and physically separates the first and second source/drain regions from one another. The channel region has a second doping type opposite the first doping type. A conductive gate electrode straddles the fin about the channel region and is separated from the channel region by a gate dielectric. A shallow doped region, which has the first doping type, is disposed near a surface of the fin around upper and sidewall fin regions. The shallow doped region extends continuously under the gate electrode between outer edges of the gate electrode.

Abstract translation: 一些实施例涉及包括一个或多个finFET器件的集成电路（IC）。 finFET包括从半导体衬底向上延伸的半导体材料的鳍。 具有第一掺杂类型的第一和第二源极/漏极区域在翅片中彼此间隔开。 沟道区域设置在翅片中并且将第一和第二源极/漏极区彼此物理分离。 沟道区具有与第一掺杂类型相反的第二掺杂型。 导电栅极电极跨过沟道区域的鳍状物并且通过栅极电介质与沟道区域分离。 具有第一掺杂类型的浅掺杂区域设置在翅片周围的上侧壁和侧壁翅片区域附近。 浅掺杂区域在栅电极的外边缘之间的栅电极下连续延伸。

公开(公告)号：US09570561B2

公开(公告)日：2017-02-14

申请号：US14179601

申请日：2014-02-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Yi-Ju Chen ,  Sheng-Fu Yu ,  I-Shan Huang ,  Kuan Yu Chen ,  Li-Yi Chen

IPC: H01L29/36 ,  H01L29/78 ,  H01L27/088 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/36 ,  H01L21/26586 ,  H01L27/0886 ,  H01L29/1041 ,  H01L29/66803 ,  H01L29/7854 ,  H01L2029/7858

Abstract: Some embodiments relate to an integrated circuit (IC) including one or more finFET devices. A finFET includes a fin of semiconductor material extending upwards from a semiconductor substrate. First and second source/drain regions, which have a first doping type, are spaced apart laterally from one another in the fin. A channel region is disposed in the fin and physically separates the first and second source/drain regions from one another. The channel region has a second doping type opposite the first doping type. A conductive gate electrode straddles the fin about the channel region and is separated from the channel region by a gate dielectric. A shallow doped region, which has the first doping type, is disposed near a surface of the fin around upper and sidewall fin regions. The shallow doped region extends continuously under the gate electrode between outer edges of the gate electrode.

Abstract translation: 一些实施例涉及包括一个或多个finFET器件的集成电路（IC）。 finFET包括从半导体衬底向上延伸的半导体材料的鳍。 具有第一掺杂类型的第一和第二源极/漏极区域在翅片中彼此间隔开。 沟道区域设置在翅片中并且将第一和第二源极/漏极区彼此物理分离。 沟道区具有与第一掺杂类型相反的第二掺杂型。 导电栅极电极跨过沟道区域的鳍状物并且通过栅极电介质与沟道区域分离。 具有第一掺杂类型的浅掺杂区域设置在翅片周围的上侧壁和侧壁翅片区域附近。 浅掺杂区域在栅电极的外边缘之间的栅电极下连续延伸。

公开(公告)号：US20160035726A1

公开(公告)日：2016-02-04

申请号：US14880454

申请日：2015-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Chien-Hsun Lin ,  Sheng-Fu Yu ,  Yu-Chang Liang ,  Kuan Yu Chen ,  Li-Yi Chen

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/04

CPC classification number: H01L27/0886 ,  H01L29/04 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/7853 ,  H01L29/7854

Abstract: A FinFET device includes a dielectric layer formed over a semiconductor substrate and having an upper dielectric layer surface. A fin of semiconductor material extends upwards from the substrate through an opening in the dielectric layer. A base portion of the fin, which is recessed below the upper dielectric layer surface, includes a base channel region that separates first and second base source/drain regions. An upper channel region extends upwards from the base channel region and terminates in an upper fin surface disposed above the upper dielectric layer surface. A gate electrode straddles the upper channel region and is separated from the upper channel region by a gate dielectric. First and second epitaxial source/drain regions meet the first and second base source/drain regions, respectively, at first and second interfaces, respectively. The first and second interfaces are recessed in the opening and arranged below the upper dielectric layer surface.

公开(公告)号：US20150279975A1

公开(公告)日：2015-10-01

申请号：US14225912

申请日：2014-03-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Chien-Hsun Lin ,  Sheng-Fu Yu ,  Yu-Chang Liang ,  Kuan Yu Chen ,  Li-Yi Chen

IPC: H01L29/66 ,  H01L29/10 ,  H01L27/088

CPC classification number: H01L27/0886 ,  H01L29/04 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/7853 ,  H01L29/7854

Abstract: A FinFET device includes a dielectric layer formed over a semiconductor substrate and having an upper dielectric layer surface. A fin of semiconductor material extends upwards from the substrate through an opening in the dielectric layer. A base portion of the fin, which is recessed below the upper dielectric layer surface, includes a base channel region that separates first and second base source/drain regions. An upper channel region extends upwards from the base channel region and terminates in an upper fin surface disposed above the upper dielectric layer surface. A gate electrode straddles the upper channel region and is separated from the upper channel region by a gate dielectric. First and second epitaxial source/drain regions meet the first and second base source/drain regions, respectively, at first and second interfaces, respectively. The first and second interfaces are recessed in the opening and arranged below the upper dielectric layer surface.

Abstract translation: FinFET器件包括形成在半导体衬底上并具有上电介质层表面的电介质层。 半导体材料的翅片从基板向上延伸穿过电介质层中的开口。 鳍状物的底部凹陷在上介电层表面下方，包括分隔第一和第二基极/漏极区的基极沟道区。 上通道区域从基通道区域向上延伸并且终止于设置在上电介质层表面上方的上散热片表面。 栅电极跨越上沟道区，并通过栅极电介质与上沟道区分离。 第一和第二外延源极/漏极区分别在第一和第二界面处分别与第一和第二基极源极/漏极区域相交。 第一和第二接口凹入开口并且布置在上电介质层表面的下方。

公开(公告)号：US20240387536A1

公开(公告)日：2024-11-21

申请号：US18788931

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsi-Jung Wu ,  Sheng-Fu Yu ,  Ru-Shang Hsiao ,  Ying-Hsin Lu

IPC: H01L27/088 ,  H01L21/762 ,  H01L29/66

Abstract: An embodiment includes a semiconductor device, a plurality of fin structures extending from a substrate, the plurality of fin structures having a plurality of first fin structures and a plurality of second fin structures. The semiconductor device also includes a plurality of isolation regions on the substrate and disposed between the plurality of fin structures. The device also includes a plurality of gate structures on the plurality of isolation regions. The device also includes a plurality of epitaxy structures on one of the plurality of first fin structures. The device also includes a plurality of contact structures on the plurality of epitaxy structures, where the plurality of first fin structures, the plurality of gate structures, the plurality of epitaxy structures, and the plurality of contact structures are components of one or more resonators.

公开(公告)号：US09490254B2

公开(公告)日：2016-11-08

申请号：US14880454

申请日：2015-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Chien-Hsun Lin ,  Sheng-Fu Yu ,  Yu-Chang Liang ,  Kuan Yu Chen ,  Li-Yi Chen

IPC: H01L29/76 ,  H01L21/84 ,  H01L27/088 ,  H01L29/66 ,  H01L29/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L29/04 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/7853 ,  H01L29/7854

Abstract: A FinFET device includes a dielectric layer formed over a semiconductor substrate and having an upper dielectric layer surface. A fin of semiconductor material extends upwards from the substrate through an opening in the dielectric layer. A base portion of the fin, which is recessed below the upper dielectric layer surface, includes a base channel region that separates first and second base source/drain regions. An upper channel region extends upwards from the base channel region and terminates in an upper fin surface disposed above the upper dielectric layer surface. A gate electrode straddles the upper channel region and is separated from the upper channel region by a gate dielectric. First and second epitaxial source/drain regions meet the first and second base source/drain regions, respectively, at first and second interfaces, respectively. The first and second interfaces are recessed in the opening and arranged below the upper dielectric layer surface.

公开(公告)号：US09252233B2

公开(公告)日：2016-02-02

申请号：US14205971

申请日：2014-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Rou-Han Kuo ,  Ting-Fu Lin ,  Sheng-Fu Yu ,  Tzung-Da Liu ,  Li-Yi Chen

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/49

CPC classification number: H01L29/515 ,  H01L21/311 ,  H01L21/823431 ,  H01L21/823468 ,  H01L29/165 ,  H01L29/4991 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure relates to a method of forming a FinFET device having sidewalls spacers comprising an air gap that provides for a low dielectric constant, and an associated apparatus. In some embodiments, the method is performed by forming a fin of semiconductor material on a semiconductor substrate. A gate structure, having a gate dielectric layer and an overlying gate material layer, is formed at a position overlying the fin of semiconductor material. Sidewall spacers are formed at positions abutting opposing sides of the gate structure. Respective sidewall spacers have a first layer of insulating material abutting the gate structure and a second layer of insulating material separated from the first layer of insulating material by an air gap. By forming the FinFET device to have sidewall spacers with air gaps, the parasitic capacitance of the FinFET device and a corresponding RC time delay are decreased.

Abstract translation: 本公开涉及一种形成具有侧壁间隔件的FinFET器件的方法，所述侧壁间隔件包括提供低介电常数的气隙和相关联的器件。 在一些实施例中，该方法通过在半导体衬底上形成半导体材料的翅片来执行。 在覆盖半导体材料的鳍片的位置处形成具有栅极介电层和覆盖栅极材料层的栅极结构。 侧壁间隔件形成在与栅极结构的相对侧相邻的位置处。 相应的侧壁间隔物具有邻接栅极结构的第一绝缘材料层和通过气隙与第一绝缘材料层分离的第二绝缘材料层。 通过形成具有气隙的侧壁间隔物的FinFET器件，FinFET器件的寄生电容和相应的RC时间延迟减小。

公开(公告)号：US09159812B1

公开(公告)日：2015-10-13

申请号：US14225912

申请日：2014-03-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Chien-Hsun Lin ,  Sheng-Fu Yu ,  Yu-Chang Liang ,  Kuan Yu Chen ,  Li-Yi Chen

IPC: H01L21/84 ,  H01L29/76 ,  H01L29/66 ,  H01L27/088 ,  H01L29/10

CPC classification number: H01L27/0886 ,  H01L29/04 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/7853 ,  H01L29/7854

Abstract: A FinFET device includes a dielectric layer formed over a semiconductor substrate and having an upper dielectric layer surface. A fin of semiconductor material extends upwards from the substrate through an opening in the dielectric layer. A base portion of the fin, which is recessed below the upper dielectric layer surface, includes a base channel region that separates first and second base source/drain regions. An upper channel region extends upwards from the base channel region and terminates in an upper fin surface disposed above the upper dielectric layer surface. A gate electrode straddles the upper channel region and is separated from the upper channel region by a gate dielectric. First and second epitaxial source/drain regions meet the first and second base source/drain regions, respectively, at first and second interfaces, respectively. The first and second interfaces are recessed in the opening and arranged below the upper dielectric layer surface.

Abstract translation: FinFET器件包括形成在半导体衬底上并具有上电介质层表面的电介质层。 半导体材料的翅片从基板向上延伸穿过电介质层中的开口。 鳍状物的底部凹陷在上介电层表面下方，包括分隔第一和第二基极/漏极区的基极沟道区。 上通道区域从基通道区域向上延伸并且终止于设置在上电介质层表面上方的上散热片表面。 栅电极跨越上沟道区，并通过栅极电介质与上沟道区分离。 第一和第二外延源极/漏极区分别在第一和第二界面处分别与第一和第二基极源极/漏极区域相交。 第一和第二接口凹入开口并且布置在上电介质层表面的下方。

公开(公告)号：US20150263122A1

公开(公告)日：2015-09-17

申请号：US14205971

申请日：2014-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Rou-Han Kuo ,  Ting-Fu Lin ,  Sheng-Fu Yu ,  Tzung-Da Liu ,  Li-Yi Chen

IPC: H01L29/51 ,  H01L29/66 ,  H01L21/311 ,  H01L29/78

CPC classification number: H01L29/515 ,  H01L21/311 ,  H01L21/823431 ,  H01L21/823468 ,  H01L29/165 ,  H01L29/4991 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure relates to a method of forming a FinFET device having sidewalls spacers comprising an air gap that provides for a low dielectric constant, and an associated apparatus. In some embodiments, the method is performed by forming a fin of semiconductor material on a semiconductor substrate. A gate structure, having a gate dielectric layer and an overlying gate material layer, is formed at a position overlying the fin of semiconductor material. Sidewall spacers are formed at positions abutting opposing sides of the gate structure. Respective sidewall spacers have a first layer of insulating material abutting the gate structure and a second layer of insulating material separated from the first layer of insulating material by an air gap. By forming the FinFET device to have sidewall spacers with air gaps, the parasitic capacitance of the FinFET device and a corresponding RC time delay are decreased.

Abstract translation: 本公开涉及一种形成具有侧壁间隔件的FinFET器件的方法，所述侧壁间隔件包括提供低介电常数的气隙和相关联的器件。 在一些实施例中，该方法通过在半导体衬底上形成半导体材料的翅片来执行。 在覆盖半导体材料的鳍片的位置处形成具有栅极介电层和覆盖栅极材料层的栅极结构。 侧壁间隔件形成在与栅极结构的相对侧相邻的位置处。 各侧壁间隔物具有邻接栅极结构的第一绝缘材料层和通过气隙与第一绝缘材料层分离的第二绝缘材料层。 通过形成具有气隙的侧壁间隔物的FinFET器件，FinFET器件的寄生电容和相应的RC时间延迟减小。