公开(公告)号：US09252233B2

公开(公告)日：2016-02-02

申请号：US14205971

申请日：2014-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Rou-Han Kuo ,  Ting-Fu Lin ,  Sheng-Fu Yu ,  Tzung-Da Liu ,  Li-Yi Chen

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/49

CPC classification number: H01L29/515 ,  H01L21/311 ,  H01L21/823431 ,  H01L21/823468 ,  H01L29/165 ,  H01L29/4991 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure relates to a method of forming a FinFET device having sidewalls spacers comprising an air gap that provides for a low dielectric constant, and an associated apparatus. In some embodiments, the method is performed by forming a fin of semiconductor material on a semiconductor substrate. A gate structure, having a gate dielectric layer and an overlying gate material layer, is formed at a position overlying the fin of semiconductor material. Sidewall spacers are formed at positions abutting opposing sides of the gate structure. Respective sidewall spacers have a first layer of insulating material abutting the gate structure and a second layer of insulating material separated from the first layer of insulating material by an air gap. By forming the FinFET device to have sidewall spacers with air gaps, the parasitic capacitance of the FinFET device and a corresponding RC time delay are decreased.

Abstract translation: 本公开涉及一种形成具有侧壁间隔件的FinFET器件的方法，所述侧壁间隔件包括提供低介电常数的气隙和相关联的器件。 在一些实施例中，该方法通过在半导体衬底上形成半导体材料的翅片来执行。 在覆盖半导体材料的鳍片的位置处形成具有栅极介电层和覆盖栅极材料层的栅极结构。 侧壁间隔件形成在与栅极结构的相对侧相邻的位置处。 相应的侧壁间隔物具有邻接栅极结构的第一绝缘材料层和通过气隙与第一绝缘材料层分离的第二绝缘材料层。 通过形成具有气隙的侧壁间隔物的FinFET器件，FinFET器件的寄生电容和相应的RC时间延迟减小。

公开(公告)号：US20150263122A1

公开(公告)日：2015-09-17

申请号：US14205971

申请日：2014-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Rou-Han Kuo ,  Ting-Fu Lin ,  Sheng-Fu Yu ,  Tzung-Da Liu ,  Li-Yi Chen

IPC: H01L29/51 ,  H01L29/66 ,  H01L21/311 ,  H01L29/78

CPC classification number: H01L29/515 ,  H01L21/311 ,  H01L21/823431 ,  H01L21/823468 ,  H01L29/165 ,  H01L29/4991 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure relates to a method of forming a FinFET device having sidewalls spacers comprising an air gap that provides for a low dielectric constant, and an associated apparatus. In some embodiments, the method is performed by forming a fin of semiconductor material on a semiconductor substrate. A gate structure, having a gate dielectric layer and an overlying gate material layer, is formed at a position overlying the fin of semiconductor material. Sidewall spacers are formed at positions abutting opposing sides of the gate structure. Respective sidewall spacers have a first layer of insulating material abutting the gate structure and a second layer of insulating material separated from the first layer of insulating material by an air gap. By forming the FinFET device to have sidewall spacers with air gaps, the parasitic capacitance of the FinFET device and a corresponding RC time delay are decreased.

Abstract translation: 本公开涉及一种形成具有侧壁间隔件的FinFET器件的方法，所述侧壁间隔件包括提供低介电常数的气隙和相关联的器件。 在一些实施例中，该方法通过在半导体衬底上形成半导体材料的翅片来执行。 在覆盖半导体材料的鳍片的位置处形成具有栅极介电层和覆盖栅极材料层的栅极结构。 侧壁间隔件形成在与栅极结构的相对侧相邻的位置处。 各侧壁间隔物具有邻接栅极结构的第一绝缘材料层和通过气隙与第一绝缘材料层分离的第二绝缘材料层。 通过形成具有气隙的侧壁间隔物的FinFET器件，FinFET器件的寄生电容和相应的RC时间延迟减小。