公开(公告)号：US20250046679A1

公开(公告)日：2025-02-06

申请号：US18526498

申请日：2023-12-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hsun Lin

IPC: H01L23/48 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522

Abstract: In an embodiment, a method includes: forming a first opening in a semiconductor substrate, in a plan view the first opening having a ring shape; forming a dielectric guard ring in the first opening; forming an active device along a first surface of the semiconductor substrate; forming first metallization layers over the active device; forming a second opening through the semiconductor substrate, the second opening adjacent to the ring shape of the dielectric guard ring; forming a conductive through via in the second opening; and forming second metallization layers over the first metallization layers.

公开(公告)号：US20160035726A1

公开(公告)日：2016-02-04

申请号：US14880454

申请日：2015-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Chien-Hsun Lin ,  Sheng-Fu Yu ,  Yu-Chang Liang ,  Kuan Yu Chen ,  Li-Yi Chen

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/04

CPC classification number: H01L27/0886 ,  H01L29/04 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/7853 ,  H01L29/7854

Abstract: A FinFET device includes a dielectric layer formed over a semiconductor substrate and having an upper dielectric layer surface. A fin of semiconductor material extends upwards from the substrate through an opening in the dielectric layer. A base portion of the fin, which is recessed below the upper dielectric layer surface, includes a base channel region that separates first and second base source/drain regions. An upper channel region extends upwards from the base channel region and terminates in an upper fin surface disposed above the upper dielectric layer surface. A gate electrode straddles the upper channel region and is separated from the upper channel region by a gate dielectric. First and second epitaxial source/drain regions meet the first and second base source/drain regions, respectively, at first and second interfaces, respectively. The first and second interfaces are recessed in the opening and arranged below the upper dielectric layer surface.

公开(公告)号：US20150279975A1

公开(公告)日：2015-10-01

申请号：US14225912

申请日：2014-03-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Chien-Hsun Lin ,  Sheng-Fu Yu ,  Yu-Chang Liang ,  Kuan Yu Chen ,  Li-Yi Chen

IPC: H01L29/66 ,  H01L29/10 ,  H01L27/088

CPC classification number: H01L27/0886 ,  H01L29/04 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/7853 ,  H01L29/7854

Abstract: A FinFET device includes a dielectric layer formed over a semiconductor substrate and having an upper dielectric layer surface. A fin of semiconductor material extends upwards from the substrate through an opening in the dielectric layer. A base portion of the fin, which is recessed below the upper dielectric layer surface, includes a base channel region that separates first and second base source/drain regions. An upper channel region extends upwards from the base channel region and terminates in an upper fin surface disposed above the upper dielectric layer surface. A gate electrode straddles the upper channel region and is separated from the upper channel region by a gate dielectric. First and second epitaxial source/drain regions meet the first and second base source/drain regions, respectively, at first and second interfaces, respectively. The first and second interfaces are recessed in the opening and arranged below the upper dielectric layer surface.

Abstract translation: FinFET器件包括形成在半导体衬底上并具有上电介质层表面的电介质层。 半导体材料的翅片从基板向上延伸穿过电介质层中的开口。 鳍状物的底部凹陷在上介电层表面下方，包括分隔第一和第二基极/漏极区的基极沟道区。 上通道区域从基通道区域向上延伸并且终止于设置在上电介质层表面上方的上散热片表面。 栅电极跨越上沟道区，并通过栅极电介质与上沟道区分离。 第一和第二外延源极/漏极区分别在第一和第二界面处分别与第一和第二基极源极/漏极区域相交。 第一和第二接口凹入开口并且布置在上电介质层表面的下方。

公开(公告)号：US09490254B2

公开(公告)日：2016-11-08

申请号：US14880454

申请日：2015-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Chien-Hsun Lin ,  Sheng-Fu Yu ,  Yu-Chang Liang ,  Kuan Yu Chen ,  Li-Yi Chen

IPC: H01L29/76 ,  H01L21/84 ,  H01L27/088 ,  H01L29/66 ,  H01L29/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L29/04 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/7853 ,  H01L29/7854

Abstract: A FinFET device includes a dielectric layer formed over a semiconductor substrate and having an upper dielectric layer surface. A fin of semiconductor material extends upwards from the substrate through an opening in the dielectric layer. A base portion of the fin, which is recessed below the upper dielectric layer surface, includes a base channel region that separates first and second base source/drain regions. An upper channel region extends upwards from the base channel region and terminates in an upper fin surface disposed above the upper dielectric layer surface. A gate electrode straddles the upper channel region and is separated from the upper channel region by a gate dielectric. First and second epitaxial source/drain regions meet the first and second base source/drain regions, respectively, at first and second interfaces, respectively. The first and second interfaces are recessed in the opening and arranged below the upper dielectric layer surface.

公开(公告)号：US09159812B1

公开(公告)日：2015-10-13

申请号：US14225912

申请日：2014-03-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Chien-Hsun Lin ,  Sheng-Fu Yu ,  Yu-Chang Liang ,  Kuan Yu Chen ,  Li-Yi Chen

IPC: H01L21/84 ,  H01L29/76 ,  H01L29/66 ,  H01L27/088 ,  H01L29/10

CPC classification number: H01L27/0886 ,  H01L29/04 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/7853 ,  H01L29/7854

Abstract: A FinFET device includes a dielectric layer formed over a semiconductor substrate and having an upper dielectric layer surface. A fin of semiconductor material extends upwards from the substrate through an opening in the dielectric layer. A base portion of the fin, which is recessed below the upper dielectric layer surface, includes a base channel region that separates first and second base source/drain regions. An upper channel region extends upwards from the base channel region and terminates in an upper fin surface disposed above the upper dielectric layer surface. A gate electrode straddles the upper channel region and is separated from the upper channel region by a gate dielectric. First and second epitaxial source/drain regions meet the first and second base source/drain regions, respectively, at first and second interfaces, respectively. The first and second interfaces are recessed in the opening and arranged below the upper dielectric layer surface.

Abstract translation: FinFET器件包括形成在半导体衬底上并具有上电介质层表面的电介质层。 半导体材料的翅片从基板向上延伸穿过电介质层中的开口。 鳍状物的底部凹陷在上介电层表面下方，包括分隔第一和第二基极/漏极区的基极沟道区。 上通道区域从基通道区域向上延伸并且终止于设置在上电介质层表面上方的上散热片表面。 栅电极跨越上沟道区，并通过栅极电介质与上沟道区分离。 第一和第二外延源极/漏极区分别在第一和第二界面处分别与第一和第二基极源极/漏极区域相交。 第一和第二接口凹入开口并且布置在上电介质层表面的下方。