公开(公告)号：US20230378305A1

公开(公告)日：2023-11-23

申请号：US18227731

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Li WANG ,  Hsu-Kai Chang ,  Jhih-Rong Huang ,  Yen-Tien Tung ,  Chia-Hung Chu ,  Tzer-Min Shen ,  Pinyen Lin

IPC: H01L29/45 ,  H01L21/285 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/45 ,  H01L21/28518 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7851 ,  H01L21/823418 ,  H01L29/7839

Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure disposed on the substrate, a gate structure disposed on the fin structure, a source/drain (S/D) region disposed adjacent to the gate structure, a contact structure disposed on the S/D region, and a dipole layer disposed at an interface between the ternary compound layer and the S/D region. The contact structure includes a ternary compound layer disposed on the S/D region, a work function metal (WFM) silicide layer disposed on the ternary compound layer, and a contact plug disposed on the WFM silicide layer.

公开(公告)号：US20230012147A1

公开(公告)日：2023-01-12

申请号：US17371245

申请日：2021-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hung CHU ,  Ding-Kang SHIH ,  Keng-Chu LIN ,  Pang-Yen TSAI ,  Sung-Li WANG ,  Shuen-Shin LIANG ,  Tsungyu HUNG ,  Hsu-Kai CHANG

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/40 ,  H01L21/285

Abstract: The present disclosure describes a method to form a semiconductor device with backside contact structures. The method includes forming a semiconductor device on a first side of a substrate. The semiconductor device includes a source/drain (S/D) region. The method further includes etching a portion of the S/D region on a second side of the substrate to form an opening and forming an epitaxial contact structure on the S/D region in the opening. The second side is opposite to the first side. The epitaxial contact structure includes a first portion in contact with the S/D region in the opening and a second portion on the first portion. A width of the second portion is larger than the first portion.

公开(公告)号：US20220384601A1

公开(公告)日：2022-12-01

申请号：US17818918

申请日：2022-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Hsu-Kai CHANG ,  Jhih-Rong HUANG ,  Yen-Tien TUNG ,  Chia-Hung CHU ,  Shuen-Shin LIANG ,  Tzer-Min SHEN ,  Pinyen LIN ,  Sung-Li WANG

IPC: H01L29/45 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/78

Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.

公开(公告)号：US20210407925A1

公开(公告)日：2021-12-30

申请号：US16950537

申请日：2020-11-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei CHANG ,  Chien-Shun LIAO ,  Sung-Li WANG ,  Shuen-Shin LIANG ,  Shu-Lan CHANG ,  Yi-Ying LIU ,  Chia-Hung CHU ,  Hsu-Kai CHANG

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/768

Abstract: The present disclosure describes a method for the fabrication of ruthenium conductive structures over cobalt conductive structures. In some embodiments, the method includes forming a first opening in a dielectric layer to expose a first cobalt contact and filling the first opening with ruthenium metal to form a ruthenium contact on the first cobalt contact. The method also includes forming a second opening in the dielectric layer to expose a second cobalt contact and a gate structure and filling the second opening with tungsten to form a tungsten contact on the second cobalt contact and the gate structure. Further, the method includes forming a copper conductive structure on the ruthenium contact and the tungsten contact, where the copper from the copper conductive structure is in contact with the ruthenium metal from the ruthenium contact.

公开(公告)号：US20210202399A1

公开(公告)日：2021-07-01

申请号：US16945595

申请日：2020-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Wei CHANG ,  Chia-Hung CHU ,  Kao-Feng LIN ,  Hsu-Kai CHANG ,  Shuen-Shin LIANG ,  Sung-Li WANG ,  Yi-Ying LIU ,  Po-Nan YEH ,  Yu Shih WANG ,  U-Ting CHIU ,  Chun-Neng LIN ,  Ming-Hsi YEH

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768

Abstract: A semiconductor device includes a gate electrode, a source/drain structure, a lower contact contacting either of the gate electrode or the source/drain structure, and an upper contact disposed in an opening formed in an interlayer dielectric (ILD) layer and in direct contact with the lower contact. The upper contact is in direct contact with the ILD layer without an interposing conductive barrier layer, and the upper contact includes ruthenium.

公开(公告)号：US20200350314A1

公开(公告)日：2020-11-05

申请号：US16927799

申请日：2020-07-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Sung-Li WANG ,  Pang-Yen TSAI ,  Yasutoshi OKUNO

IPC: H01L27/092 ,  H01L29/45 ,  H01L21/8238 ,  H01L29/08 ,  H01L21/02 ,  H01L21/768 ,  H01L29/78

Abstract: A semiconductor device includes first and second epitaxial structures, first and second top metal alloy layers, and first and second bottom metal alloy layers. The first and second epitaxial structures have different cross sections. The first and second top metal alloy layers are respectively in contact with the first and second epitaxial structures. The first and second bottom metal alloy layers are respectively in contact with the first and second epitaxial structures and respectively under the first and second top metal alloy layers. The first top metal alloy layer and the first bottom metal alloy layer are made of different materials.

公开(公告)号：US20200273695A1

公开(公告)日：2020-08-27

申请号：US16283109

申请日：2019-02-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mrunal A. KHADERBAD ,  Keng-Chu LIN ,  Shuen-Shin LIANG ,  Sung-Li WANG ,  Yasutoshi OKUNO ,  Yu-Yun PENG

IPC: H01L21/02 ,  H01L21/768

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a dielectric structure on a semiconductor substrate, introducing a first gas on the dielectric structure to form first conductive structures on the dielectric structure, and introducing a second gas on the first conductive structures and the dielectric structure. The second gas is different from the first gas. The method also includes introducing a third gas on the first conductive structures and the dielectric structure to form second conductive structures on the dielectric structure. The first gas and the third gas include the same metal.

公开(公告)号：US20240088261A1

公开(公告)日：2024-03-14

申请号：US18516410

申请日：2023-11-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Peng-Wei CHU ,  Yasutoshi OKUNO ,  Ding-Kang SHIH ,  Sung-Li WANG

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/165 ,  H01L29/45

CPC classification number: H01L29/665 ,  H01L21/0206 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/6656 ,  H01L21/02576 ,  H01L21/02579

Abstract: The structure of a semiconductor device with dual silicide contact structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming first and second fin structures on a substrate, forming first and second epitaxial regions on the first and second fin structures, respectively, forming first and second contact openings on the first and second epitaxial regions, respectively, selectively forming an oxide capping layer on exposed surfaces of the second epitaxial region, selectively forming a first metal silicide layer on exposed surfaces of the first epitaxial region, removing the oxide capping layer, and forming first and second conductive regions on the metal silicide layer and on the exposed surfaces of the second epitaxial region, respectively. The first metal silicide layer includes a first metal. The first and second conductive regions includes a second metal different from the first metal.

公开(公告)号：US20230163169A1

公开(公告)日：2023-05-25

申请号：US18158148

申请日：2023-01-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei CHANG ,  Shuen-Shin LIANg ,  Sung-Li WANG ,  Hsu-Kai CHANG ,  Chia-Hung CHU ,  Chien-Shun LIAO ,  Yi-Ying LIU

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/417 ,  H01L29/10

CPC classification number: H01L29/0665 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/41733 ,  H01L29/1033

Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and methods of fabricating the same are disclosed. The semiconductor device includes first and second S/D regions, a nanostructured channel region disposed between the first and second S/D regions, a gate structure surrounding the nanostructured channel region, first and second contact structures disposed on first surfaces of the first and second S/D regions, a third contact structure disposed on a second surface of the first S/D region, and an etch stop layer disposed on a second surface of the second S/D region. The third contact structure includes a metal silicide layer, a silicide nitride layer disposed on the metal silicide layer, and a conductive layer disposed on the silicide nitride layer.

公开(公告)号：US20230095976A1

公开(公告)日：2023-03-30

申请号：US18061676

申请日：2022-12-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shuen-Shin LIANG ,  Chun-I TSAI ,  Chih-Wei CHANG ,  Chun-Hsien HUANG ,  Hung-Yi HUANG ,  Keng-Chu LIN ,  Ken-Yu CHANG ,  Sung-Li WANG ,  Chia-Hung CHU ,  Hsu-Kai CHANG

IPC: H01L23/532 ,  H01L21/768

Abstract: The present disclosure describes a method for forming capping layers configured to prevent the migration of out-diffused cobalt atoms into upper metallization layers In some embodiments, the method includes depositing a cobalt diffusion barrier layer on a liner-free conductive structure that includes ruthenium, where depositing the cobalt diffusion barrier layer includes forming the cobalt diffusion barrier layer self-aligned to the liner-free conductive structure. The method also includes depositing, on the cobalt diffusion barrier layer, a stack with an etch stop layer and dielectric layer, and forming an opening in the stack to expose the cobalt diffusion barrier layer. Finally, the method includes forming a conductive structure on the cobalt diffusion barrier layer.