公开(公告)号：US20230163169A1

公开(公告)日：2023-05-25

申请号：US18158148

申请日：2023-01-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei CHANG ,  Shuen-Shin LIANg ,  Sung-Li WANG ,  Hsu-Kai CHANG ,  Chia-Hung CHU ,  Chien-Shun LIAO ,  Yi-Ying LIU

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/417 ,  H01L29/10

CPC classification number: H01L29/0665 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/41733 ,  H01L29/1033

Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and methods of fabricating the same are disclosed. The semiconductor device includes first and second S/D regions, a nanostructured channel region disposed between the first and second S/D regions, a gate structure surrounding the nanostructured channel region, first and second contact structures disposed on first surfaces of the first and second S/D regions, a third contact structure disposed on a second surface of the first S/D region, and an etch stop layer disposed on a second surface of the second S/D region. The third contact structure includes a metal silicide layer, a silicide nitride layer disposed on the metal silicide layer, and a conductive layer disposed on the silicide nitride layer.

公开(公告)号：US20240096998A1

公开(公告)日：2024-03-21

申请号：US18516373

申请日：2023-11-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shuen-Shin LIANG ,  Chij-chien CHI ,  Yi-Ying LIU ,  Chia-Hung CHU ,  Hsu-Kai CHANG ,  Cheng-Wei CHANG ,  Chein-Shun LIAO ,  Keng-chu LIN ,  KAi-Ting HUANG

IPC: H01L29/45 ,  H01L21/768 ,  H01L23/532 ,  H01L23/535 ,  H01L29/78

CPC classification number: H01L29/45 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76882 ,  H01L21/76895 ,  H01L23/53209 ,  H01L23/535 ,  H01L29/7851

Abstract: The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.

公开(公告)号：US20210407925A1

公开(公告)日：2021-12-30

申请号：US16950537

申请日：2020-11-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei CHANG ,  Chien-Shun LIAO ,  Sung-Li WANG ,  Shuen-Shin LIANG ,  Shu-Lan CHANG ,  Yi-Ying LIU ,  Chia-Hung CHU ,  Hsu-Kai CHANG

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/768

Abstract: The present disclosure describes a method for the fabrication of ruthenium conductive structures over cobalt conductive structures. In some embodiments, the method includes forming a first opening in a dielectric layer to expose a first cobalt contact and filling the first opening with ruthenium metal to form a ruthenium contact on the first cobalt contact. The method also includes forming a second opening in the dielectric layer to expose a second cobalt contact and a gate structure and filling the second opening with tungsten to form a tungsten contact on the second cobalt contact and the gate structure. Further, the method includes forming a copper conductive structure on the ruthenium contact and the tungsten contact, where the copper from the copper conductive structure is in contact with the ruthenium metal from the ruthenium contact.

公开(公告)号：US20210202399A1

公开(公告)日：2021-07-01

申请号：US16945595

申请日：2020-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Wei CHANG ,  Chia-Hung CHU ,  Kao-Feng LIN ,  Hsu-Kai CHANG ,  Shuen-Shin LIANG ,  Sung-Li WANG ,  Yi-Ying LIU ,  Po-Nan YEH ,  Yu Shih WANG ,  U-Ting CHIU ,  Chun-Neng LIN ,  Ming-Hsi YEH

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768

Abstract: A semiconductor device includes a gate electrode, a source/drain structure, a lower contact contacting either of the gate electrode or the source/drain structure, and an upper contact disposed in an opening formed in an interlayer dielectric (ILD) layer and in direct contact with the lower contact. The upper contact is in direct contact with the ILD layer without an interposing conductive barrier layer, and the upper contact includes ruthenium.