公开(公告)号：US07733714B2

公开(公告)日：2010-06-08

申请号：US12139550

申请日：2008-06-16

申请人： Tadahiko Horiuchi ,  Kenji Noda

发明人： Tadahiko Horiuchi ,  Kenji Noda

IPC分类号： G11C7/00

CPC分类号： G11C11/5671 ,  G11C2211/5642 ,  G11C2211/5647

摘要： A memory circuit includes a latch having a first node and a second node to store data such that a logic level of the first node is an inverse of a logic level of the second node, a MIS transistor having a gate node, a first source/drain node, and a second source/drain node, the first source/drain node coupled to the first node of the latch, and a control circuit configured to control the gate node and second source/drain node of the MIS transistor to make an upward lingering change in a threshold voltage of the MIS transistor in a first operation in response to data stored in the latch and to make a downward lingering change in the threshold voltage in a second operation in response to data stored in the latch.

摘要翻译： 存储器电路包括具有第一节点和第二节点的锁存器，用于存储数据，使得第一节点的逻辑电平为第二节点的逻辑电平的倒数，具有门节点的MIS晶体管，第一源/ 漏极节点和第二源极/漏极节点，耦合到锁存器的第一节点的第一源极/漏极节点以及控制电路，被配置为控制MIS晶体管的栅极节点和第二源极/漏极节点向上 响应于存储在锁存器中的数据，在第一操作中MIS晶体管的阈值电压的持续变化，并且响应于存储在锁存器中的数据，在第二操作中使阈值电压下降。

公开(公告)号：US20090310428A1

公开(公告)日：2009-12-17

申请号：US12139550

申请日：2008-06-16

申请人： Tadahiko Horiuchi ,  Kenji Noda

发明人： Tadahiko Horiuchi ,  Kenji Noda

IPC分类号： G11C7/00

CPC分类号： G11C11/5671 ,  G11C2211/5642 ,  G11C2211/5647

摘要： A memory circuit includes a latch having a first node and a second node to store data such that a logic level of the first node is an inverse of a logic level of the second node, a MIS transistor having a gate node, a first source/drain node, and a second source/drain node, the first source/drain node coupled to the first node of the latch, and a control circuit configured to control the gate node and second source/drain node of the MIS transistor to make an upward lingering change in a threshold voltage of the MIS transistor in a first operation in response to data stored in the latch and to make a downward lingering change in the threshold voltage in a second operation in response to data stored in the latch.

摘要翻译： 存储器电路包括具有第一节点和第二节点的锁存器，用于存储数据，使得第一节点的逻辑电平为第二节点的逻辑电平的倒数，具有门节点的MIS晶体管，第一源极/ 漏极节点和第二源极/漏极节点，耦合到锁存器的第一节点的第一源极/漏极节点以及控制电路，被配置为控制MIS晶体管的栅极节点和第二源极/漏极节点向上 响应于存储在锁存器中的数据，在第一操作中MIS晶体管的阈值电压的持续变化，并且响应于存储在锁存器中的数据，在第二操作中使阈值电压下降。

公开(公告)号：US07821806B2

公开(公告)日：2010-10-26

申请号：US12141231

申请日：2008-06-18

申请人： Tadahiko Horiuchi

发明人： Tadahiko Horiuchi

IPC分类号： G11C17/12

CPC分类号： G11C11/412 ,  G11C14/00 ,  H01L21/28282 ,  H01L27/11565 ,  H01L29/792

摘要： A memory circuit includes a latch having a first node and a second node to store data such that a logic level of the first node is an inverse of a logic level of the second node, a MIS transistor having a gate node, a first source/drain node, and a second source/drain node, the first source/drain node coupled to the first node of the latch, and a control circuit configured to control the gate node and second source/drain node of the MIS transistor in a first operation such that a lingering change is created in transistor characteristics of the MIS transistor in response to the data stored in the latch, wherein the MIS transistor includes a highly-doped substrate layer, a lightly-doped substrate layer disposed on the highly-doped substrate layer, diffusion regions formed in the lightly-doped substrate layer, a gate electrode, sidewalls, and an insulating film.

摘要翻译： 存储器电路包括具有第一节点和第二节点的锁存器，用于存储数据，使得第一节点的逻辑电平为第二节点的逻辑电平的倒数，具有门节点的MIS晶体管，第一源极/ 漏极节点和第二源极/漏极节点，耦合到锁存器的第一节点的第一源极/漏极节点以及被配置为在第一操作中控制MIS晶体管的栅极节点和第二源极/漏极节点的控制电路 使得响应于存储在锁存器中的数据在MIS晶体管的晶体管特性中产生延迟的变化，其中，MIS晶体管包括高掺杂衬底层，设置在高掺杂衬底层上的轻掺杂衬底层 形成在轻掺杂衬底层中的扩散区，栅电极，侧壁和绝缘膜。

公开(公告)号：US06372628B1

公开(公告)日：2002-04-16

申请号：US09579474

申请日：2000-05-26

申请人： Yoshihisa Matsubara ,  Ko Noguchi ,  Shinya Ito ,  Noriaki Oda ,  Akira Matsumoto ,  Takashi Ishigami ,  Masahiko Nakamae ,  Tadahiko Horiuchi ,  Kazuhiko Endo ,  Toru Tatsumi ,  Yoshishige Matsumoto

发明人： Yoshihisa Matsubara ,  Ko Noguchi ,  Shinya Ito ,  Noriaki Oda ,  Akira Matsumoto ,  Takashi Ishigami ,  Masahiko Nakamae ,  Tadahiko Horiuchi ,  Kazuhiko Endo ,  Toru Tatsumi ,  Yoshishige Matsumoto

IPC分类号： H01L214763

CPC分类号： H01L21/02118 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/312 ,  H01L21/3185 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/53223 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure and manufacturing process of a low dielectric constant interlayer insulating film used between wiring layers and semiconductor devices using such film are disclosed. The insulating film which can withstand in an actual process comprises an amorphous carbon fluoride film. A diamond like carbon film and a silicon excess layer are disposed on both sides of the amorphous carbon fluoride film to be inserted between the wiring layers, whereby adhesion to wiring and another insulating film contacting it is significantly enhanced. In addition, a silicon based insulating film is disposed and flattened on a multilayer film containing an amorphous carbon fluoride film buried with a wiring layer, and is used as a hard mask for anisotropically etching the diamond like carbon film and the amorphous carbon fluoride film with oxygen plasma to form a via hole.

摘要翻译： 公开了在布线层和使用这种膜的半导体器件之间使用的低介电常数层间绝缘膜的结构和制造工艺。 可以在实际工艺中承受的绝缘膜包括无定形氟化碳膜。 在无定形氟化碳膜的两侧设置有类金刚石碳膜和硅过剩层，以插入布线层之间，从而显着提高与布线的接合和与其接触的另一绝缘膜。 另外，将硅基绝缘膜设置并平坦化在含有埋设有布线层的无定形氟化碳膜的多层膜上，并且用作用于各向异性蚀刻金刚石状碳膜和无定形氟化碳膜的硬掩模， 氧等离子体形成通孔。

公开(公告)号：US08451657B2

公开(公告)日：2013-05-28

申请号：US13026720

申请日：2011-02-14

申请人： Tadahiko Horiuchi

发明人： Tadahiko Horiuchi

IPC分类号： G11C11/34

CPC分类号： G11C7/02 ,  G11C8/08 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/28

摘要： A nonvolatile semiconductor memory device includes an MIS transistor having nodes, a control circuit configured to apply a first set of potentials to the nodes to cause an irreversible change in transistor characteristics, to apply a second set of potentials to the nodes to cause a first current to flow through the MIS transistor in a first direction, and to apply the second set of potentials to the nodes to cause a second current to flow through the MIS transistor in a second direction opposite the first direction, and a sense circuit configured to produce a signal responsive to a difference between the first current and the second current.

摘要翻译： 非易失性半导体存储器件包括具有节点的MIS晶体管，控制电路被配置为将第一组电势施加到节点以引起晶体管特性的不可逆变化，以将第二组电势施加到节点以引起第一电流 在第一方向上流过MIS晶体管，并且将第二组电势施加到节点，以使第二电流在与第一方向相反的第二方向上流过MIS晶体管;以及感测电路，其被配置为产生 响应于第一电流和第二电流之间的差异的信号。

公开(公告)号：US20120114531A1

公开(公告)日：2012-05-10

申请号：US13383298

申请日：2010-05-27

申请人： Takashi Higuchi ,  Tadahiko Horiuchi

发明人： Takashi Higuchi ,  Tadahiko Horiuchi

IPC分类号： B01D53/76

CPC分类号： C30B15/20 ,  C30B15/00 ,  C30B29/06 ,  C30B35/00 ,  F27B14/08 ,  F27D17/008

摘要： A silicon oxide removal apparatus for removing silicon oxide contained in an inert gas discharged from a silicon single crystal manufacturing apparatus, including at least: a contact means for bringing the inert gas discharged from the silicon single crystal manufacturing apparatus into contact with a strongly alkaline solution; and a neutralizing means for neutralizing an alkaline material contained in the inert gas brought into contact with the strongly alkaline solution. As a result, there is provided a silicon oxide removal apparatus and a facility for recycling an inert gas for use in a silicon single crystal manufacturing apparatus that can more effectively remove the silicon oxide contained in the inert gas discharged from the silicon single crystal manufacturing apparatus at low cost and enable recycle of the inert gas in which the silicon oxide has been effectively removed.

摘要翻译： 一种用于去除从单晶硅制造装置排出的惰性气体中所含的氧化硅的氧化硅去除装置，至少包括：将从硅单晶制造装置排出的惰性气体与强碱性溶液接触的接触装置 ; 以及用于中和与强碱性溶液接触的惰性气体中所含的碱性物质的中和装置。 结果，提供了一种氧化硅去除装置和用于再循环用于硅单晶制造装置中的惰性气体的设备，其可以更有效地去除从硅单晶制造装置排出的惰性气体中所含的氧化硅 并且能够使已经有效除去氧化硅的惰性气体再循环。

公开(公告)号：US07791927B1

公开(公告)日：2010-09-07

申请号：US12372780

申请日：2009-02-18

申请人： Tadahiko Horiuchi

发明人： Tadahiko Horiuchi

IPC分类号： G11C11/00 ,  G11C11/34

CPC分类号： G11C16/0466 ,  H01L21/28282 ,  H01L29/7923

摘要： A memory circuit includes a latch having a first node and a second node, a MIS transistor having a gate node, a first source/drain node coupled to the first node of the latch, and a second source/drain node, and a control circuit configured to control the gate node and second source/drain node to make a lingering change in a threshold voltage of the MIS transistor in a first operation and to cause the latch in a second operation to store data responsive to whether a lingering change in the threshold voltage is present, wherein the MIS transistor includes diffusion regions, a gate electrode, and sidewalls, wherein a metallurgical junction of each of the diffusion regions is positioned under the gate electrode, and a lateral boundary of a depletion layer in the diffusion region serving as a drain is positioned under a corresponding one of the sidewalls in the first operation.

摘要翻译： 存储器电路包括具有第一节点和第二节点的锁存器，具有栅极节点的MIS晶体管，耦合到锁存器的第一节点的第一源极/漏极节点和第二源极/漏极节点以及控制电路 被配置为在第一操作中控制所述栅极节点和所述第二源极/漏极节点以使所述MIS晶体管的阈值电压发生延迟的变化，并且使所述锁存器在第二操作中存储数据，以响应所述阈值的延迟变化 存在电压，其中，所述MIS晶体管包括扩散区域，栅电极和侧壁，其中，所述扩散区域中的每一个的冶金结点位于所述栅电极下方，并且所述扩散区域中的耗尽层的横向边界用作 在第一操作中，漏极位于相应的一个侧壁下方。

公开(公告)号：US20090316477A1

公开(公告)日：2009-12-24

申请号：US12141231

申请日：2008-06-18

申请人： Tadahiko Horiuchi

发明人： Tadahiko Horiuchi

IPC分类号： G11C11/34 ,  G11C7/00

CPC分类号： G11C11/412 ,  G11C14/00 ,  H01L21/28282 ,  H01L27/11565 ,  H01L29/792

摘要： A memory circuit includes a latch having a first node and a second node to store data such that a logic level of the first node is an inverse of a logic level of the second node, a MIS transistor having a gate node, a first source/drain node, and a second source/drain node, the first source/drain node coupled to the first node of the latch, and a control circuit configured to control the gate node and second source/drain node of the MIS transistor in a first operation such that a lingering change is created in transistor characteristics of the MIS transistor in response to the data stored in the latch, wherein the MIS transistor includes a highly-doped substrate layer, a lightly-doped substrate layer disposed on the highly-doped substrate layer, diffusion regions formed in the lightly-doped substrate layer, a gate electrode, sidewalls, and an insulating film.

摘要翻译： 存储器电路包括具有第一节点和第二节点的锁存器，用于存储数据，使得第一节点的逻辑电平为第二节点的逻辑电平的倒数，具有门节点的MIS晶体管，第一源极/ 漏极节点和第二源极/漏极节点，耦合到锁存器的第一节点的第一源极/漏极节点以及被配置为在第一操作中控制MIS晶体管的栅极节点和第二源极/漏极节点的控制电路 使得响应于存储在锁存器中的数据在MIS晶体管的晶体管特性中产生延迟的变化，其中，MIS晶体管包括高掺杂衬底层，设置在高掺杂衬底层上的轻掺杂衬底层 形成在轻掺杂衬底层中的扩散区，栅电极，侧壁和绝缘膜。

公开(公告)号：US5286664A

公开(公告)日：1994-02-15

申请号：US955356

申请日：1992-10-01

申请人： Tadahiko Horiuchi

发明人： Tadahiko Horiuchi

IPC分类号： H01L21/316 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/6659 ,  H01L21/316 ,  H01L21/823468 ,  H01L27/0922 ,  H01L29/66659 ,  H01L29/7835

摘要： A process of fabricating an asymmetrical LDD-MOSFET of the type in which a diffused low-doped layer is provided only on the drain side is disclosed. In a MOSFET-formed region, after forming a gate electrode, using a photoresist film covering one sidewall of the gate electrode and the vicinity thereof, ion implantation is performed to form a diffused lightly-doped layer and thereover a silicon dioxide film is selectively grown by the liquid phase deposition technique. In detail, immersion of a concerned wafer in a silicon dioxide-saturated hydrofluosilicic acid aqueous solution while adding boric acid to it brings about the separation and deposition of silicon dioxide film. No deposition onto the surface of the photoresist film takes place. In usual way proceeds formation of a spacer by anisotropic etching, followed by heavily doped source and drain regions. A reduced source parasitic resistance LDD-MOSFET can be easily fabricated.

摘要翻译： 公开了一种制造其中扩散低掺杂层仅在漏极侧提供的类型的不对称LDD-MOSFET的工艺。 在MOSFET形成区域中，在形成栅电极之后，使用覆盖栅电极的一个侧壁及其附近的光致抗蚀剂膜，进行离子注入以形成漫射的轻掺杂层，并且选择性地生长二氧化硅膜 通过液相沉积技术。 详细地，将相关晶片浸入二氧化硅饱和的氢氟硅酸水溶液中，同时向其中加入硼酸导致二氧化硅膜的分离和沉积。 不会在光致抗蚀剂膜的表面上沉积。 以通常的方式通过各向异性蚀刻形成间隔物，随后是重掺杂的源极和漏极区。 可以容易地制造降低的源寄生电阻LDD-MOSFET。

公开(公告)号：US20070014145A1

公开(公告)日：2007-01-18

申请号：US11180132

申请日：2005-07-13

申请人： Tadahiko Horiuchi

发明人： Tadahiko Horiuchi

IPC分类号： G11C11/00

CPC分类号： G11C16/0466 ,  G11C16/10

摘要： A memory circuit includes a latch having a first node and a second node, a plate line, a word selecting line, a first MIS transistor having source/drain nodes thereof coupled to the first node and the plate line, respectively, and a gate node thereof coupled to the word selecting line, a second MIS transistor having source/drain nodes thereof coupled to the second node and the plate line, respectively, and a gate node thereof coupled to the word selecting line, and a driver configured to set the plate line to a first potential causing a current to flow in a first direction through the first MIS transistor in a first operation mode and to a second potential causing a current to flow in a second direction through the first MIS transistor in a second operation mode, the first operation mode causing a lingering change in characteristics of the first MIS transistor.