A memory circuit includes a latch having a first node and a second node, a MIS transistor having a gate node, a first source/drain node coupled to the first node of the latch, and a second source/drain node, and a control circuit configured to control the gate node and second source/drain node to make a lingering change in a threshold voltage of the MIS transistor in a first operation and to cause the latch in a second operation to store data responsive to whether a lingering change in the threshold voltage is present, wherein the MIS transistor includes diffusion regions, a gate electrode, and sidewalls, wherein a metallurgical junction of each of the diffusion regions is positioned under the gate electrode, and a lateral boundary of a depletion layer in the diffusion region serving as a drain is positioned under a corresponding one of the sidewalls in the first operation.