公开(公告)号：US20240170074A1

公开(公告)日：2024-05-23

申请号：US18091839

申请日：2022-12-30

申请人： NSCore, Inc.

发明人： Kazuhiko Oyama ,  Tadahiko Horiuchi

IPC分类号： G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30

CPC分类号： G11C16/26 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30

摘要： A semiconductor memory device includes a bit line pairs, a source line, a word line, and a memory cell array including a plurality of memory cells arranged in a row and column directions, wherein the memory cell is a pair of p-type transistors formed on an n-type well, wherein one of terminals of the transistor is a Schottky barrier junction consisting of a metal thin film formed on the n-type well, and the other terminal is connected to the source line.

公开(公告)号：US20150243348A1

公开(公告)日：2015-08-27

申请号：US14190292

申请日：2014-02-26

申请人： NSCore, Inc.

发明人： Tadahiko HORIUCHI

IPC分类号： G11C11/419 ,  G11C5/06

CPC分类号： G11C11/419 ,  G11C11/41 ,  G11C14/00 ,  G11C16/0466

摘要： A nonvolatile memory device includes a word line, four or more bit lines, three or more MIS transistors having gate nodes thereof connected to the word line, the N-th (N: positive integer) one of the MIS transistors having two source/drain nodes thereof connected to the N-th and N+1-th ones of the bit lines, respectively, a sense circuit having two nodes and configured to amplify a difference between potentials of the two nodes, and a switch circuit configured to electrically couple the N-th and N+2-th ones of the bit lines to the two nodes of the sense circuit, respectively, and to electrically couple the N+1-th one of the bit lines to a fixed potential, for any numerical number N selected to detect single-bit data stored in the N-th and N+1-th ones of the MIS transistors.

摘要翻译： 非易失性存储器件包括字线，四个或更多个位线，三个或更多个MIS晶体管，其栅极节点连接到字线，第三（N：正整数）一个MIS晶体管具有两个源极/漏极 其节点分别连接到位线的第N和第N + 1位，具有两个节点并被配置为放大两个节点的电位之间的差异的感测电路，以及被配置为电耦合 第N和第N + 2个位线分别连接到感测电路的两个节点，并且将N + 1个位线电耦合到固定电位，对于任何数字N 被选择以检测存储在第N和第N + 1个MIS晶体管中的单位数据。

公开(公告)号：US07542341B2

公开(公告)日：2009-06-02

申请号：US11841265

申请日：2007-08-20

申请人： Takashi Kikuchi

发明人： Takashi Kikuchi

IPC分类号： G11C11/34

CPC分类号： G11C11/412 ,  G11C11/413

摘要： A nonvolatile semiconductor memory device includes a first latch to store data, a nonvolatile memory cell including two MIS transistors to store data as an irreversible change of transistor characteristics occurring in one of the two MIS transistors selected in response to the data stored in the first latch, a second latch to store data obtained by sensing a difference in the transistor characteristics between the two MIS transistors, a logic circuit to produce a signal indicative of comparison between the data of the first latch and the data of the second latch, and a control circuit configured to repeat a store operation storing data in the nonvolatile memory cell, a recall operation storing data in the second latch, and a verify operation producing the signal indicative of comparison until the signal indicates that the data of the first latch and the data of the second latch are the same.

摘要翻译： 非易失性半导体存储器件包括用于存储数据的第一锁存器，包括两个MIS晶体管的非易失性存储器单元，用于将数据存储为在响应于存储在第一锁存器中的数据选择的两个MIS晶体管之一中出现的晶体管特性的不可逆变化 用于存储通过感测两个MIS晶体管之间的晶体管特性的差异获得的数据的第二锁存器，产生指示第一锁存器的数据与第二锁存器的数据之间的比较的信号的逻辑电路，以及控制 电路，被配置为重复存储在非易失性存储单元中的数据的存储操作，存储第二锁存器中的数据的调用操作，以及产生指示比较的信号的校验操作，直到信号指示第一锁存器的数据和 第二个锁存器是相同的。

公开(公告)号：US20080186767A1

公开(公告)日：2008-08-07

申请号：US11701958

申请日：2007-02-02

申请人： Takashi Kikuchi ,  Kenji Noda

发明人： Takashi Kikuchi ,  Kenji Noda

IPC分类号： G11C16/06

CPC分类号： G11C14/00 ,  G11C14/0063

摘要： A nonvolatile semiconductor memory device includes a control circuit, an inverting circuit, and memory units, each of the memory units including a latch having a first node and a second node, a plate line, a first MIS transistor having one of source/drain nodes coupled to the first node of the latch, another one of the source/drain nodes coupled to the plate line, and a gate node coupled to a word line, and a second MIS transistor having one of source/drain nodes coupled to the second node of the latch, another one of the source/drain nodes coupled to the plate line, and a gate node coupled to the word line, wherein the control circuit is configured to invert the data latched in the latch by reading the data from the latch, causing the inverting circuit to invert the read data, and writing the inverted data to the latch.

摘要翻译： 非易失性半导体存储器件包括控制电路，反相电路和存储器单元，每个存储器单元包括具有第一节点和第二节点的锁存器，板线，具有源/漏节点之一的第一MIS晶体管 耦合到锁存器的第一节点，耦合到板线的源极/漏极节点中的另一个以及耦合到字线的栅极节点以及耦合到第二节点的源极/漏极节点之一的第二MIS晶体管 耦合到板线的源/漏节点中的另一个和耦合到字线的栅极节点，其中控制电路被配置为通过从锁存器读取数据来反转锁存在锁存器中的数据， 使反相电路反转读取的数据，并将反相数据写入锁存器。

公开(公告)号：US08259505B2

公开(公告)日：2012-09-04

申请号：US12789522

申请日：2010-05-28

申请人： Kazuhiko Oyama

发明人： Kazuhiko Oyama

IPC分类号： G11C16/04 ,  G11C7/02

CPC分类号： G11C16/28

摘要： A nonvolatile memory device includes one or more reference cell transistors, one or more memory cell transistors, and a current source circuit including three or more field effect transistors that have gates thereof connected together, the three or more field effect transistors including two or more field effect transistors and another field effect transistor, currents flowing through the two or more field effect transistors being combined to flow through the one or more reference cell transistors, and another field effect transistor having a drain thereof connected to one of the one or more memory cell transistors.

摘要翻译： 非易失性存储器件包括一个或多个参考单元晶体管，一个或多个存储单元晶体管，以及包括三个或更多个其栅极连接在一起的场效应晶体管的电流源电路，所述三个或更多个场效应晶体管包括两个或更多个场 效应晶体管和另一个场效应晶体管，流经两个或更多个场效应晶体管的电流被组合以流过一个或多个参考单元晶体管，以及另一场效应晶体管，其漏极连接到一个或多个存储单元之一 晶体管。

公开(公告)号：US07835196B2

公开(公告)日：2010-11-16

申请号：US12088971

申请日：2005-10-03

申请人： Kenji Noda

发明人： Kenji Noda

IPC分类号： G11C7/10

CPC分类号： G11C16/0466 ,  G11C11/412 ,  G11C14/00 ,  G11C17/08

摘要： A nonvolatile memory device includes a pair of PMOS transistors, and a control circuit configured to operate in a store mode to apply to a first one of the PMOS transistors potentials that cause an NBTI degradation purposefully and to apply to a second one of the PMOS transistors potentials that cause no NBTI degradation while causing no current to flow between a source node and a drain node of the first one of the PMOS transistors, and to operate in a recall mode to set gate nodes of the PMOS transistors to a common potential to detect a difference in the NBTI degradation between said PMOS transistors.

摘要翻译： 非易失性存储器件包括一对PMOS晶体管，以及控制电路，其被配置为以存储模式工作，以应用于导致NBTI劣化的第一个PMOS晶体管的电位，并且施加到第二个PMOS晶体管 不导致NBTI劣化的电位，同时在PMOS晶体管的第一个源极节点和漏极节点之间没有电流流动，并且以调用模式操作以将PMOS晶体管的栅极节点设置为共同的电位来检测 所述PMOS晶体管之间的NBTI劣化的差异。

公开(公告)号：US07821806B2

公开(公告)日：2010-10-26

申请号：US12141231

申请日：2008-06-18

申请人： Tadahiko Horiuchi

发明人： Tadahiko Horiuchi

IPC分类号： G11C17/12

CPC分类号： G11C11/412 ,  G11C14/00 ,  H01L21/28282 ,  H01L27/11565 ,  H01L29/792

摘要： A memory circuit includes a latch having a first node and a second node to store data such that a logic level of the first node is an inverse of a logic level of the second node, a MIS transistor having a gate node, a first source/drain node, and a second source/drain node, the first source/drain node coupled to the first node of the latch, and a control circuit configured to control the gate node and second source/drain node of the MIS transistor in a first operation such that a lingering change is created in transistor characteristics of the MIS transistor in response to the data stored in the latch, wherein the MIS transistor includes a highly-doped substrate layer, a lightly-doped substrate layer disposed on the highly-doped substrate layer, diffusion regions formed in the lightly-doped substrate layer, a gate electrode, sidewalls, and an insulating film.

摘要翻译： 存储器电路包括具有第一节点和第二节点的锁存器，用于存储数据，使得第一节点的逻辑电平为第二节点的逻辑电平的倒数，具有门节点的MIS晶体管，第一源极/ 漏极节点和第二源极/漏极节点，耦合到锁存器的第一节点的第一源极/漏极节点以及被配置为在第一操作中控制MIS晶体管的栅极节点和第二源极/漏极节点的控制电路 使得响应于存储在锁存器中的数据在MIS晶体管的晶体管特性中产生延迟的变化，其中，MIS晶体管包括高掺杂衬底层，设置在高掺杂衬底层上的轻掺杂衬底层 形成在轻掺杂衬底层中的扩散区，栅电极，侧壁和绝缘膜。

公开(公告)号：US07639546B2

公开(公告)日：2009-12-29

申请号：US12037414

申请日：2008-02-26

申请人： Takashi Kikuchi ,  Kenji Noda

发明人： Takashi Kikuchi ,  Kenji Noda

IPC分类号： G11C7/00

CPC分类号： G11C7/1045 ,  G11C7/1006 ,  G11C7/12 ,  G11C14/00 ,  G11C14/0063

摘要： A nonvolatile semiconductor memory device includes a latch circuit having two nodes, a nonvolatile memory cell including two MIS transistors, a bit swapping unit configured to provide straight connections between the two nodes and the two MIS transistors during a first operation mode and to provide cross connections between the two nodes and the two MIS transistors during a second operation mode, and a control circuit configured to cause, in one of the first and second operation modes, the nonvolatile memory cell to store the data latched in the latch circuit as an irreversible change of transistor characteristics occurring in a selected one of the two MIS transistors, and further configured to cause, in another one of the first and second operation modes, the latch circuit to detect the data stored in the nonvolatile memory cell.

摘要翻译： 非易失性半导体存储器件包括具有两个节点的锁存电路，包括两个MIS晶体管的非易失性存储器单元，配置成在第一操作模式期间在两个节点和两个MIS晶体管之间提供直连接并提供交叉连接 在第二操作模式期间在两个节点和两个MIS晶体管之间，以及控制电路，被配置为在第一和第二操作模式之一中使得非易失性存储单元将锁存在锁存电路中的数据存储为不可逆变化 的晶体管特性出现在所述两个MIS晶体管中的所选择的一个中，并且还被配置为在所述第一和第二操作模式中的另一个中引起所述锁存电路来检测存储在所述非易失性存储单元中的数据。

公开(公告)号：US07518917B2

公开(公告)日：2009-04-14

申请号：US11775951

申请日：2007-07-11

申请人： Kenji Noda ,  Takashi Kikuchi

发明人： Kenji Noda ,  Takashi Kikuchi

IPC分类号： G11C11/34

CPC分类号： G11C14/00 ,  G11C11/412

摘要： A nonvolatile semiconductor memory device includes a latch configured to store data, a plurality of word lines, a driver configured to activate one of the plurality of word lines, and a plurality of nonvolatile memory cells coupled to the respective word lines, each of the nonvolatile memory cells coupled to the latch so as to exchange stored data with the latch upon activation of a corresponding one of the word lines, each of the nonvolatile memory cells including two MIS transistors and configured to store data as an irreversible change of transistor characteristics occurring in one of the two MIS transistors, wherein the driver includes at least one nonvolatile memory cell storing count data responsive to a number of times storing of data has been performed with respect to the plurality of nonvolatile memory cells, and is configured to activate one of the word lines indicated by the count data.

摘要翻译： 非易失性半导体存储器件包括：锁存器，被配置为存储数据，多个字线，被配置为激活多个字线中的一个字线的驱动器;以及耦合到各个字线的多个非易失性存储器单元，每个非易失性存储器件 存储器单元耦合到所述锁存器，以便在激活相应的一条字线时与所述锁存器交换存储的数据，所述非易失性存储器单元中的每一个包括两个MIS晶体管，并且被配置为将数据存储为晶体管特性的不可逆变化， 两个MIS晶体管中的一个，其中驱动器包括至少一个非易失性存储单元，其存储响应于多次数据存储的数量的计数数据，并且被配置为激活多个非易失性存储单元中的一个， 字数由计数数据表示。

公开(公告)号：US20090052229A1

公开(公告)日：2009-02-26

申请号：US11841265

申请日：2007-08-20

申请人： Takashi KIKUCHI

发明人： Takashi KIKUCHI

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  G11C11/413

摘要： A nonvolatile semiconductor memory device includes a first latch to store data, a nonvolatile memory cell including two MIS transistors to store data as an irreversible change of transistor characteristics occurring in one of the two MIS transistors selected in response to the data stored in the first latch, a second latch to store data obtained by sensing a difference in the transistor characteristics between the two MIS transistors, a logic circuit to produce a signal indicative of comparison between the data of the first latch and the data of the second latch, and a control circuit configured to repeat a store operation storing data in the nonvolatile memory cell, a recall operation storing data in the second latch, and a verify operation producing the signal indicative of comparison until the signal indicates that the data of the first latch and the data of the second latch are the same.

摘要翻译： 非易失性半导体存储器件包括用于存储数据的第一锁存器，包括两个MIS晶体管的非易失性存储器单元，用于将数据存储为在响应于存储在第一锁存器中的数据选择的两个MIS晶体管之一中出现的晶体管特性的不可逆变化 用于存储通过感测两个MIS晶体管之间的晶体管特性的差异获得的数据的第二锁存器，产生指示第一锁存器的数据与第二锁存器的数据之间的比较的信号的逻辑电路，以及控制 电路，被配置为重复存储在非易失性存储单元中的数据的存储操作，存储第二锁存器中的数据的调用操作，以及产生指示比较的信号的校验操作，直到信号指示第一锁存器的数据和 第二个锁存器是相同的。