公开(公告)号：US20240363394A1

公开(公告)日：2024-10-31

申请号：US18141153

申请日：2023-04-28

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Dong Seup Lee ,  Sunglyong Kim ,  Meng-Chia Lee ,  Satoshi Suzuki ,  Seetharaman Sridhar

IPC分类号： H01L21/761 ,  H01L27/088

CPC分类号： H01L21/761 ,  H01L27/088 ,  H01L21/2652 ,  H01L21/266 ,  H01L29/66681

摘要： Described examples include an integrated circuit having a substrate, a first doped region in the substrate having a first conductivity type, and a first epitaxial layer on the substrate, wherein the first doped region extends into the first epitaxial layer. The integrated circuit also has a second doped region in the first epitaxial layer having the first conductivity type, a second epitaxial layer on the first epitaxial layer, wherein the second doped region extends into the second epitaxial layer. The integrated circuit also has a well in the second epitaxial layer having a second conductivity type, and a first active device formed in the well.

公开(公告)号：US20210143145A1

公开(公告)日：2021-05-13

申请号：US17123413

申请日：2020-12-16

申请人： Texas Instruments Incorporated

发明人： Sunglyong Kim ,  David LaFonteese ,  Seetharaman Sridhar ,  Sameer Pendharkar

IPC分类号： H01L27/02 ,  H01L29/10 ,  H01L29/78 ,  H01L29/08

摘要： An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a bipolar transistor structure interfacing with a PN junction of a high voltage device, which is configured to discharge the ESD current during an ESD event. The bipolar transistor structure has a collector region overlapping the PN junction, a base region embedded with sufficient pinch resistance to launch the snapback protection, and an emitter region for discharging the ESD current.

公开(公告)号：US20200075576A1

公开(公告)日：2020-03-05

申请号：US16677044

申请日：2019-11-07

申请人： Texas Instruments Incorporated

发明人： Sunglyong Kim ,  David LaFonteese ,  Seetharaman Sridhar ,  Sameer Pendharkar

IPC分类号： H01L27/02 ,  H01L29/08 ,  H01L29/78 ,  H01L29/10

摘要： An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a bipolar transistor structure interfacing with a PN junction of a high voltage device, which is configured to discharge the ESD current during an ESD event. The bipolar transistor structure has a collector region overlapping the PN junction, a base region embedded with sufficient pinch resistance to launch the snapback protection, and an emitter region for discharging the ESD current.

公开(公告)号：US10573553B2

公开(公告)日：2020-02-25

申请号：US16241143

申请日：2019-01-07

申请人： Texas Instruments Incorporated

发明人： Hong Yang ,  Abbas Ali ,  Yaping Chen ,  Chao Zuo ,  Seetharaman Sridhar ,  Yunlong Liu

IPC分类号： H01L21/00 ,  H01L21/768 ,  H01L21/285 ,  H01L21/3213 ,  H01L23/532

摘要： Disclosed examples provide processes for fabricating a semiconductor product and for forming a patterned stack with an aluminum layer and a tungsten layer, including forming a first dielectric layer on a gate structure and on first and second regions of a substrate, forming a diffusion barrier layer on the first dielectric layer, forming a tungsten layer on the diffusion barrier layer, forming an aluminum layer on the tungsten layer, forming a hard mask on the aluminum layer, forming a patterned resist mask which covers the hard mask above the first region and exposes the hard mask layer above the second region, dry etching the hard mask and the aluminum layer above the second region using the patterned resist mask layer, removing the resist mask, and dry etching the tungsten layer using the hard mask layer to expose the first dielectric layer above the second region.

公开(公告)号：US10559681B2

公开(公告)日：2020-02-11

申请号：US15850854

申请日：2017-12-21

申请人： Texas Instruments Incorporated

发明人： Sunglyong Kim ,  Seetharaman Sridhar ,  Sameer Pendharkar

IPC分类号： H01L29/78 ,  H01L21/28 ,  H03K17/687 ,  H01L29/10 ,  H01L21/761 ,  H01L29/49 ,  H01L29/66 ,  H01L29/06

摘要： A lateral junction diode device includes a substrate having at least a semiconductor surface layer. A depletion-mode LDMOS device is in the semiconductor surface layer including a source, drain, and a gate above a gate dielectric, and a channel region under the gate on the gate dielectric. A drift region is between the channel region and the drain, wherein the drain also provides a cathode for the lateral junction diode device. An embedded diode includes a second cathode and an anode that is shared with the device. The embedded diode is junction isolated by an isolation region located between the anode and the source. The anode and isolation region are directly connected to the gate and the second cathode is directly connected to the source.

公开(公告)号：US20190296115A1

公开(公告)日：2019-09-26

申请号：US16042834

申请日：2018-07-23

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Ya ping Chen ,  Hong Yang ,  Peng Li ,  Seetharaman Sridhar ,  Yunlong Liu ,  Rui Liu

IPC分类号： H01L29/40 ,  H01L29/78 ,  H01L29/66

摘要： A semiconductor device includes a substrate including a semiconductor surface layer. A field plate (FP) includes a trench in the semiconductor surface layer filled with a single polysilicon layer positioned on at least one side of a power metal-oxide-semiconductor field effect transistor (power MOSFET). The power MOSFET includes a dielectric liner lining a sidewall of the trench under the polysilicon layer including a second dielectric liner on a first dielectric liner. An upper portion of the dielectric liner has a lower dielectric thickness as compared to a dielectric thickness on its lower portion. The single polysilicon layer extends continuously over the dielectric liner along both the lower portion and the upper portion. The power MOSFET includes a drain including a drain contact below a vertical drift region in the semiconductor surface layer, and a gate, body and a source above the vertical drift region.

公开(公告)号：US20170264289A1

公开(公告)日：2017-09-14

申请号：US15067928

申请日：2016-03-11

申请人： Texas Instruments Incorporated

发明人： Yongxi Zhang ,  Sameer P. Pendharkar ,  Philip L. Hower ,  Salvatore Giombanco ,  Filippo Marino ,  Seetharaman Sridhar

IPC分类号： H03K17/687 ,  H01L29/06 ,  H03K19/0185 ,  H01L27/092

CPC分类号： H03K19/018521 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1033 ,  H01L29/7816 ,  H01L29/7831 ,  H03K17/122

摘要： An integrated circuit chip includes a bimodal power N-P-Laterally Diffused Metal Oxide Semiconductor (LDMOS) device having an N-gate coupled to receive an input signal and a level shifter coupled to receive the input signal and to provide a control signal to a P-gate driver of the N-P-LDMOS device. A method of operating an N-P-LDMOS power device is also disclosed.

公开(公告)号：US09196728B2

公开(公告)日：2015-11-24

申请号：US14557648

申请日：2014-12-02

申请人： Texas Instruments Incorporated

发明人： Seetharaman Sridhar

IPC分类号： H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L29/04 ,  H01L21/3105 ,  H01L21/311

CPC分类号： H01L29/7835 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/82385 ,  H01L21/823878 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66659 ,  H01L29/7833

摘要： An integrated circuit on a rotated substrate with an LDMOS transistor. A method of enhancing the CHC performance of an LDMOS transistor by growing a second STI liner oxide. A method of enhancing the CHC performance of an LDMOS transistor building the LDMOS transistor on a rotated substrate and growing a second STI liner oxide.

摘要翻译： 在具有LDMOS晶体管的旋转衬底上的集成电路。 通过生长第二STI衬垫氧化物来增强LDMOS晶体管的CHC性能的方法。 一种增强LDMOS晶体管的CHC性能的方法，其在旋转的衬底上构建LDMOS晶体管并生长第二STI衬里氧化物。

公开(公告)号：US20150325577A1

公开(公告)日：2015-11-12

申请号：US14803759

申请日：2015-07-20

申请人： Texas Instruments Incorporated

发明人： Binghua Hu ,  Pinghai Hao ,  Sameer Pendharkar ,  Seetharaman Sridhar ,  Jarvis Jacobs

IPC分类号： H01L27/092 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417 ,  H01L29/08 ,  H01L29/45 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423

CPC分类号： H01L27/092 ,  H01L21/761 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/0883 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/408 ,  H01L29/41758 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/7836

摘要： An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a mid voltage range, may also include a high-voltage MOS transistor which operates in a third voltage range significantly higher than the low and mid voltage ranges, for example 20 to 30 volts. The high-voltage MOS transistor has a closed loop configuration, in which a drain region is surrounded by a gate, which is in turn surrounded by a source region, so that the gate does not overlap field oxide. The integrated circuit may include an n-channel version of the high-voltage MOS transistor and/or a p-channel version of the high-voltage MOS transistor. Implanted regions of the n-channel version and the p-channel version are formed concurrently with implanted regions in the first and second pluralities of MOS transistors.

摘要翻译： 包含在低电压范围内工作的第一多个MOS晶体管的集成电路和在中间电压范围内工作的第二多个MOS晶体管也可以包括高电压MOS晶体管，其操作在明显高于 低电压和中等电压范围，例如20至30伏特。 高压MOS晶体管具有闭环配置，其中漏极区域被栅极包围，栅极又被源极区域包围，使得栅极不与场氧化物重叠。 集成电路可以包括高压MOS晶体管的n沟道版本和/或高压MOS晶体管的p沟道版本。 n沟道版本和p沟道版本的注入区域与第一和第二多个MOS晶体管中的注入区域同时形成。

公开(公告)号：US08748976B1

公开(公告)日：2014-06-10

申请号：US13787044

申请日：2013-03-06

申请人： Texas Instruments Incorporated

发明人： Christopher Boguslaw Kocon ,  John Manning Savidge Neilson ,  Simon John Molloy ,  Hideaki Kawahara ,  Hong Yang ,  Seetharaman Sridhar ,  Hao Wu ,  Boling Wen

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/0649 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7802

摘要： A semiconductor device contains a vertical MOS transistor with instances of a vertical RESURF trench on opposite sides of a vertical drift region. The vertical RESURF trench contains a dielectric trench liner on sidewalls, and a lower field plate and an upper field plate above the lower field plate. The dielectric trench liner between the lower field plate and the vertical drift region is thicker than between the upper field plate and the vertical drift region. A gate is disposed over the vertical drift region and is separate from the upper field plate. The upper field plate and the lower field plate are electrically coupled to a source electrode of the vertical MOS transistor.

摘要翻译： 半导体器件包含垂直MOS晶体管，其具有在垂直漂移区域的相对侧上的垂直RESURF沟槽的实例。 垂直RESURF沟槽包含侧壁上的电介质沟槽衬垫，下场板上的下场板和上场板。 下场板和垂直漂移区之间的电介质沟槽衬垫比上场板和垂直漂移区之间厚。 栅极设置在垂直漂移区上方并与上场板分离。 上场板和下场板电耦合到垂直MOS晶体管的源电极。