公开(公告)号：US20250040171A1

公开(公告)日：2025-01-30

申请号：US18359991

申请日：2023-07-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dong Seup Lee

IPC: H01L29/778 ,  H01L23/31 ,  H01L29/20 ,  H01L29/66

Abstract: The present disclosure generally relates to a semiconductor device having a doped region underlying a gate layer and in a barrier layer. In an example, a semiconductor device includes a channel layer, a barrier layer, and a gate layer. The channel layer is over a semiconductor substrate, and the barrier layer is over the channel layer. The gate layer is over the barrier layer, and the gate layer is doped with a dopant. A first region in the barrier layer overlies a channel region in the channel layer and underlies the gate layer. The first region has a first concentration of the dopant. A second region in the barrier layer is laterally disposed from the first region. The second region has a second concentration of the dopant that is less than the first concentration.

公开(公告)号：US11888027B2

公开(公告)日：2024-01-30

申请号：US17559635

申请日：2021-12-22

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Qhalid Fareed ,  Sridhar Seetharaman ,  Jungwoo Joh ,  Chang Soo Suh

IPC: H01L29/00 ,  H01L29/08 ,  H01L29/06 ,  H01L29/20

CPC classification number: H01L29/0847 ,  H01L29/0653 ,  H01L29/2003

Abstract: An electronic device includes an one of aluminum gallium nitride, aluminum nitride, indium aluminum nitride, or indium aluminum gallium nitride back barrier layer over a buffer structure, a gallium nitride layer over the back barrier layer, a hetero-epitaxy structure over the gallium nitride layer, first and second transistors over the hetero-epitaxy structure, and a hole injector having a doped gallium nitride structure over the hetero-epitaxy structure and a conductive structure partially over the doped gallium nitride structure to inject holes to form a hole layer proximate an interface of the back barrier layer and the buffer structure to mitigate vertical electric field back gating effects for the first transistor.

公开(公告)号：US20220231156A1

公开(公告)日：2022-07-21

申请号：US17499462

申请日：2021-10-12

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Jungwoo Joh

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/66

Abstract: A microelectronic device includes a GaN FET on a substrate such as silicon and a buffer layer of III-N semiconductor material. The GaN FET includes both source contacts and drain contacts to a channel layer of III-N semiconductor material. Source contacts to the source region are placed farther from the gate electrode fingertip than drain contacts to the drain region.

公开(公告)号：US20220181466A1

公开(公告)日：2022-06-09

申请号：US17110811

申请日：2020-12-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nicholas Stephen Dellas ,  Dong Seup Lee ,  Andinet Tefera Desalegn

IPC: H01L29/66 ,  H01L29/778 ,  H01L21/02 ,  H01L29/205 ,  H01L29/207 ,  H01L29/06

Abstract: In a described example, an integrated circuit (IC) is disclosed that includes a transistor. The transistor includes a substrate, and a buffer structure overlying the substrate. The buffer structure has a first buffer layer, a second buffer layer overlying the first buffer layer, and a third buffer layer overlying the second buffer layer. The first buffer layer has a first carbon concentration, the second buffer layer has a second carbon concentration lower than the first carbon concentration, and the third buffer layer has a third carbon concentration higher than the second carbon concentration. An active structure overlies the buffer structure.

公开(公告)号：US11067620B2

公开(公告)日：2021-07-20

申请号：US16400336

申请日：2019-05-01

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Jungwoo Joh ,  Pinghai Hao ,  Sameer Pendharkar

IPC: G01R31/26 ,  G01R27/26

Abstract: A method includes applying a DC stress condition to a transistor for a predetermined stress time, measuring an impedance of the transistor after the predetermined stress time, and repeating the application of the DC stress condition and the measurement of the impedance until the measured impedance exceeds an impedance threshold or a total stress time exceeds a time threshold, where the DC stress condition includes applying a non-zero drain voltage signal to a drain terminal of the transistor, applying a gate voltage signal to a gate terminal of the transistor, and applying a non-zero source current signal to a source terminal of the transistor.

公开(公告)号：US10964803B2

公开(公告)日：2021-03-30

申请号：US16194794

申请日：2018-11-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dong Seup Lee ,  Jungwoo Joh ,  Pinghai Hao ,  Sameer Pendharkar

IPC: H01L29/778 ,  H01L29/08 ,  H01L29/66 ,  H01L29/20 ,  H01L29/06 ,  H01L29/10 ,  H01L21/265 ,  H01L29/417 ,  H01L29/423

Abstract: In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer; and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.

公开(公告)号：US20180190550A1

公开(公告)日：2018-07-05

申请号：US15439191

申请日：2017-02-22

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Jungwoo Joh ,  Sameer Pendharkar

IPC: H01L21/66 ,  H01L29/06 ,  H01L23/544 ,  H01L29/40 ,  H01L29/20 ,  H01L29/417 ,  H01L27/088 ,  G01R31/12 ,  G01R31/28

CPC classification number: H01L22/34 ,  G01R31/12 ,  G01R31/2884 ,  H01L23/544 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/41725

Abstract: A first set of test structures for a gallium nitride (GaN) transistor that includes N field plates is disclosed, where N is an integer and X is an integer between 0 and N inclusive. A test structure TSX of the first set of test structures includes a GaN substrate, a dielectric material overlying the GaN substrate, a respective source contact abutting the GaN substrate and a respective drain contact abutting the GaN substrate. The test structure TSX also includes a respective gate overlying the substrate and lying between the respective source contact and the respective drain contact and X respective field plates corresponding to X of the N field plates of the GaN transistor, the X respective field plates including field plates that are nearest to the GaN substrate.

公开(公告)号：US20240405078A1

公开(公告)日：2024-12-05

申请号：US18326698

申请日：2023-05-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ujwal Radhakrishna ,  Yoganand Saripalli ,  Johan Strydom ,  Zhikai Tang ,  Dong Seup Lee

IPC: H01L29/20 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778

Abstract: The present disclosure generally relates to integrated devices with a conductive barrier structure. In an example, a semiconductor device includes a substrate, a conductive barrier structure, a channel layer, a barrier layer, a gate, and a conductive structure. The substrate is of a first semiconductor material. The conductive barrier structure is on the substrate. The channel layer is of a second semiconductor material and is on the conductive barrier structure. The barrier layer is on the channel layer, and the channel layer is between the barrier layer and the conductive barrier structure. The gate is over the barrier layer opposing the channel layer. The conductive structure is electrically coupled between the conductive barrier structure, the channel layer, and the barrier layer.

公开(公告)号：US20230101543A1

公开(公告)日：2023-03-30

申请号：US17491259

申请日：2021-09-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dong Seup Lee ,  Jungwoo Joh ,  Chang Soo Suh

IPC: H01L29/40

Abstract: One example described herein includes an integrated circuit (IC) that includes a gallium-nitride (GaN) transistor device. The IC includes GaN active layers that define an active region, and a gate structure arranged on a surface of the active region. The IC also includes a source arranged on a first side of the gate structure and a drain arranged on a second side of the gate structure. The IC further includes at least one source field-plate structure conductively coupled to the source and a gate-level field-plate structure that is coupled to the source.

公开(公告)号：US11527619B2

公开(公告)日：2022-12-13

申请号：US17115562

申请日：2020-12-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dong Seup Lee

IPC: H01L29/20 ,  H01L29/06 ,  H01L29/51

Abstract: A semiconductor structure includes a first transistor including a gate structure, a drain, and a source. The gate structure of the first transistor includes a nitride-based semiconductor layer. The semiconductor structure further includes a second transistor including a gate structure, a drain, and a source. The gate structure of the second transistor also includes a nitride-based semiconductor layer. The nitride-based semiconductor layer of the first transistor's gate structure is continuous with the nitride-based semiconductor layer of the second transistor's gate structure.