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    METHODS AND APPARATUS TO IMPROVE PERFORMANCE OF POWER PATH PROTECTION DEVICES
    2.
    发明申请
    METHODS AND APPARATUS TO IMPROVE PERFORMANCE OF POWER PATH PROTECTION DEVICES 有权

    公开(公告)号：US20210066909A1

    公开(公告)日：2021-03-04

    申请号：US17011522

    申请日：2020-09-03

    Applicant: Texas Instruments Incorporated

    Inventor： Yogesh Kumar Ramadass ,  Ujwal Radhakrishna ,  Jeffrey Morroni

    IPC: H02H7/20 ,  H01L23/525 ,  H03K17/687

    Abstract: An example integrated circuit includes: a substrate and a first metal fuse layer on the substrate, the first metal fuse layer having first and second electrical contacts, the first electrical contact adapted to be coupled to an input terminal, the second electrical contact adapted to be coupled to a diode. The example integrated circuit further includes a second metal fuse layer on the substrate, the second metal fuse layer having third and fourth electrical contacts, the third electrical contact coupled to the second electrical contact and adapted to be coupled to the diode, the fourth electrical contact coupled to a shunt circuit.

    INTEGRATED DEVICES WITH CONDUCTIVE BARRIER STRUCTURE
    3.
    发明申请
    INTEGRATED DEVICES WITH CONDUCTIVE BARRIER STRUCTURE 有权

    公开(公告)号：US20240405024A1

    公开(公告)日：2024-12-05

    申请号：US18534056

    申请日：2023-12-08

    Applicant: Texas Instruments Incorporated

    Inventor： Ujwal Radhakrishna ,  Yoganand Saripalli ,  Zhikai Tang ,  Timothy Merkin ,  Jungwoo Joh

    IPC: H01L27/095 ,  H01L27/02 ,  H01L29/20 ,  H01L29/778

    Abstract: The present disclosure generally relates to integrated devices with a conductive barrier structure. In an example, a semiconductor device includes a substrate, a conductive barrier structure, a channel layer, a barrier layer, a gate, and a conductive structure. The substrate is of a first semiconductor material. The conductive barrier structure is on the substrate. The channel layer is of a second semiconductor material and is on the conductive barrier structure. The barrier layer is on the channel layer, and the channel layer is between the barrier layer and the conductive barrier structure. The gate is over the barrier layer opposing the channel layer. The conductive structure is electrically coupled between the conductive barrier structure, the channel layer, and the barrier layer.

    SEMICONDUCTOR DEVICE WITH GATE ELECTRICAL CONTACT FORMING JUNCTIONS HAVING DIFFERENT ENERGY BARRIER HEIGHTS TO GATE LAYER
    5.
    发明申请
    SEMICONDUCTOR DEVICE WITH GATE ELECTRICAL CONTACT FORMING JUNCTIONS HAVING DIFFERENT ENERGY BARRIER HEIGHTS TO GATE LAYER 有权

    公开(公告)号：US20250048667A1

    公开(公告)日：2025-02-06

    申请号：US18361997

    申请日：2023-07-31

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Ujwal Radhakrishna ,  Zhikai Tang ,  Johan Strydom ,  Jungwoo Joh

    IPC: H01L29/778 ,  H01L29/40 ,  H01L29/423 ,  H01L29/45 ,  H01L29/47 ,  H01L29/872

    Abstract: The present disclosure generally relates to a semiconductor device that includes a gate electrical contact that forms junctions with different energy barrier heights to a gate layer. In an example, a semiconductor device includes a semiconductor substrate, a drain electrical contact, a source electrical contact, a barrier layer, a gate layer, and a gate electrical contact. The drain and source electrical contacts are on the semiconductor substrate. The barrier layer is over a channel region of the semiconductor substrate between the drain and source electrical contacts. The gate layer is over the barrier layer. The gate layer includes first and second semiconductor portions. The gate electrical contact contacts the gate layer. The gate electrical contact includes first and second metal portions. The first and second metal portions form first and second junctions with the first and second semiconductor portions, respectively. The first and second junctions have different energy barrier heights.

    Semiconductor doped region with biased isolated members
    7.
    发明授权
    Semiconductor doped region with biased isolated members 有权

    公开(公告)号：US12211807B2

    公开(公告)日：2025-01-28

    申请号：US18490866

    申请日：2023-10-20

    Applicant: Texas Instruments Incorporated

    Inventor： Alexei Sadovnikov ,  Sheldon Douglas Haynie ,  Ujwal Radhakrishna

    IPC: H01L23/64 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

    Abstract: A microelectronic device includes a doped region of semiconductor material having a first region and an opposite second region. The microelectronic device is configured to provide a first operational potential at the first region and to provide a second operational potential at the second region. The microelectronic device includes field plate segments in trenches extending into the doped region. Each field plate segment is separated from the semiconductor material by a trench liner of dielectric material. The microelectronic device further includes circuitry electrically connected to each of the field plate segments. The circuitry is configured to apply bias potentials to the field plate segments. The bias potentials are monotonic with respect to distances of the field plate segments from the first region of the doped region.

    Fail-open isolator
    8.
    发明授权
    Fail-open isolator 有权

    公开(公告)号：US12183672B2

    公开(公告)日：2024-12-31

    申请号：US17677729

    申请日：2022-02-22

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Ujwal Radhakrishna ,  Vinod Rai ,  Yogesh Ramadass ,  Anant Kamath ,  Kashyap Barot

    IPC: H01L23/525 ,  H02H3/04

    Abstract: A device includes first and second device terminals, a fuse, a first circuit, a first transistor, and a control circuit. The fuse terminal couples to the first device terminal. The first circuit couples to the second fuse terminal. The second fuse terminal has a first voltage. The first transistor has a first control input and first and second current terminals. The first current terminal couples to the second fuse terminal, and the second current terminal couples to the second device terminal. The control circuit: turns “on” the first transistor into a saturation region if the first voltage exceeds a threshold and a current through the fuse exceeds a trip threshold current of the fuse; and turns “on” the first transistor into a linear region if the first voltage exceeds a threshold and a current through the fuse is below the trip threshold current of the fuse.

    INTEGRATED DEVICES WITH CONDUCTIVE BARRIER STRUCTURE
    10.
    发明申请
    INTEGRATED DEVICES WITH CONDUCTIVE BARRIER STRUCTURE 有权

    公开(公告)号：US20240405078A1

    公开(公告)日：2024-12-05

    申请号：US18326698

    申请日：2023-05-31

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Ujwal Radhakrishna ,  Yoganand Saripalli ,  Johan Strydom ,  Zhikai Tang ,  Dong Seup Lee

    IPC: H01L29/20 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778

    Abstract: The present disclosure generally relates to integrated devices with a conductive barrier structure. In an example, a semiconductor device includes a substrate, a conductive barrier structure, a channel layer, a barrier layer, a gate, and a conductive structure. The substrate is of a first semiconductor material. The conductive barrier structure is on the substrate. The channel layer is of a second semiconductor material and is on the conductive barrier structure. The barrier layer is on the channel layer, and the channel layer is between the barrier layer and the conductive barrier structure. The gate is over the barrier layer opposing the channel layer. The conductive structure is electrically coupled between the conductive barrier structure, the channel layer, and the barrier layer.

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