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    Systems and methods for producing flat surfaces in interconnect structures
    2.
    发明授权
    Systems and methods for producing flat surfaces in interconnect structures 有权

    公开(公告)号：US10199275B2

    公开(公告)日：2019-02-05

    申请号：US15716165

    申请日：2017-09-26

    Applicant: TESSERA, INC.

    Inventor： Cyprian Uzoh ,  Vage Oganesian ,  Ilyas Mohammed

    IPC: H01L21/4763 ,  H01L21/768 ,  H01L21/321 ,  H01L23/48 ,  H01L23/532

    Abstract: In interconnect fabrication (e.g. a damascene process), a conductive layer is formed over a substrate with holes, and is polished to provide interconnect features in the holes. To prevent erosion/dishing of the conductive layer at the holes, the conductive layer is covered by a sacrificial layer (possibly conformal) before polishing; then both layers are polished. Initially, before polishing, the conductive layer and the sacrificial layer are recessed over the holes, but the sacrificial layer is polished at a lower rate to result in a protrusion of the conductive layer at a location of each hole. The polishing can continue to remove the protrusions and provide a planar surface.

    Systems and methods for producing flat surfaces in interconnect structures
    4.
    发明授权
    Systems and methods for producing flat surfaces in interconnect structures 有权
    用于在互连结构中产生平坦表面的系统和方法

    公开(公告)号：US09558998B2

    公开(公告)日：2017-01-31

    申请号：US15066238

    申请日：2016-03-10

    Applicant: Tessera, Inc.

    Inventor： Cyprian Uzoh ,  Vage Oganesian ,  Ilyas Mohammed

    IPC: H01L21/4763 ,  H01L21/768 ,  H01L21/321 ,  H01L23/48

    CPC classification number: H01L21/76898 ,  H01L21/3212 ,  H01L21/32125 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/7688 ,  H01L23/481 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In interconnect fabrication (e.g. a damascene process), a conductive layer is formed over a substrate with holes, and is polished to provide interconnect features in the holes. To prevent erosion/dishing of the conductive layer at the holes, the conductive layer is covered by a sacrificial layer (possibly conformal) before polishing; then both layers are polished. Initially, before polishing, the conductive layer and the sacrificial layer are recessed over the holes, but the sacrificial layer is polished at a lower rate to result in a protrusion of the conductive layer at a location of each hole. The polishing can continue to remove the protrusions and provide a planar surface.

    Abstract translation: 在互连制造（例如镶嵌工艺）中，在具有孔的衬底上形成导电层，并且被抛光以在孔中提供互连特征。 为了防止导电层在孔处的侵蚀/凹陷，在抛光之前，导电层被牺牲层（可能保形）覆盖; 然后两层都被抛光。 最初，在抛光之前，导电层和牺牲层在孔上凹陷，但牺牲层以较低的速率被抛光，导致导电层在每个孔的位置处突出。 抛光可以继续移除突起并提供平坦的表面。

    Systems and methods for producing flat surfaces in interconnect structures
    7.
    发明授权
    Systems and methods for producing flat surfaces in interconnect structures 有权
    用于在互连结构中产生平坦表面的系统和方法

    公开(公告)号：US09123703B2

    公开(公告)日：2015-09-01

    申请号：US14199181

    申请日：2014-03-06

    Applicant: Tessera, Inc.

    Inventor： Cyprian Uzoh ,  Vage Oganesian ,  Iiyas Mohammed

    IPC: H01L23/48 ,  H01L21/768 ,  H01L21/321

    CPC classification number: H01L21/76898 ,  H01L21/3212 ,  H01L21/32125 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/7688 ,  H01L23/481 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a co-planar or flat top surface. Another feature is a method of forming an interconnect structure that results in the interconnect structure having a surface that is angled upwards greater than zero with respect to a top surface of the substrate. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.

    Abstract translation: 提供了用于形成半导体器件的方法和装置，其可以包括任何数量的特征。 一个特征是形成互连结构的方法，其导致互连结构具有共面或平坦的顶表面。 另一个特征是形成互连结构的方法，其导致互连结构具有相对于衬底顶表面向上倾斜大于零的表面。 互连结构可以包括镶嵌结构，例如单镶嵌结构或双镶嵌结构，或者可以包括硅通孔（TSV）结构。

    SYSTEMS AND METHODS FOR PRODUCING FLAT SURFACES IN INTERCONNECT STRUCTURES
    9.
    发明申请
    SYSTEMS AND METHODS FOR PRODUCING FLAT SURFACES IN INTERCONNECT STRUCTURES 有权
    用于在互连结构中生产平面表面的系统和方法

    公开(公告)号：US20140210102A1

    公开(公告)日：2014-07-31

    申请号：US14199181

    申请日：2014-03-06

    Applicant: Tessera, Inc.

    Inventor： Cyprian Uzoh ,  Vage Oganesian ,  liyas Mohammed

    IPC: H01L23/48

    CPC classification number: H01L21/76898 ,  H01L21/3212 ,  H01L21/32125 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/7688 ,  H01L23/481 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a co-planar or flat top surface. Another feature is a method of forming an interconnect structure that results in the interconnect structure having a surface that is angled upwards greater than zero with respect to a top surface of the substrate. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.

    Abstract translation: 提供了用于形成半导体器件的方法和装置，其可以包括任何数量的特征。 一个特征是形成互连结构的方法，其导致互连结构具有共面或平坦的顶表面。 另一个特征是形成互连结构的方法，其导致互连结构具有相对于衬底顶表面向上倾斜大于零的表面。 互连结构可以包括镶嵌结构，例如单镶嵌结构或双镶嵌结构，或者可以包括硅通孔（TSV）结构。

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