公开(公告)号：US12081215B2

公开(公告)日：2024-09-03

申请号：US18333284

申请日：2023-06-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yu-Lun Ou ,  Ji-Yung Lin ,  Yung-Chen Chien ,  Ruei-Wun Sun ,  Wei-Hsiang Ma ,  Jerry Chang Jui Kao ,  Shang-Chih Hsieh ,  Lee-Chung Lu

IPC: H03K3/037 ,  H03K19/0185

CPC classification number: H03K19/018521 ,  H03K3/037

Abstract: A circuit includes an input circuit, a level shifter circuit, an output circuit, and a first and a second feedback circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate at least a second input signal. The level shifter circuit is coupled to a second voltage supply, and configured to generate at least a first and second signal responsive to at least the enable signal or the first input signal. The output circuit is coupled to at least the level shifter circuit and the second voltage supply, and configured to generate at least an output signal, a first and second feedback signal responsive to the first signal. The first and second feedback circuit are configured to receive the enable signal, and the inverted enable signal, and the corresponding first and second feedback signal.

公开(公告)号：US20240071941A1

公开(公告)日：2024-02-29

申请号：US17897648

申请日：2022-08-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Fa Chen ,  Yun-Han Lee ,  Lee-Chung Lu

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/5386 ,  H01L21/486 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0655 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696 ,  H01L23/5385 ,  H01L2224/08225 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/13081

Abstract: A semiconductor device includes: a first chip including a plurality of first device features and a plurality of first interconnect structures disposed above the first device features; a second chip including a plurality of second device features and a plurality of second interconnect structures disposed above the second device features; and an interposer bonded to the first chip and the second chip, and disposed on an opposite side from the first and second device features with respect to the first and second interconnect structures; wherein the interposer includes a plurality of power rails configured to deliver power to the first and second chips.

公开(公告)号：US11756999B2

公开(公告)日：2023-09-12

申请号：US17205670

申请日：2021-03-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jung-Chan Yang ,  Hui-Zhong Zhuang ,  Lee-Chung Lu ,  Ting-Wei Chiang ,  Li-Chun Tien

IPC: H01L29/06 ,  H01L27/092 ,  H01L27/02 ,  H01L21/033 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  G06F30/392

CPC classification number: H01L29/0696 ,  G06F30/392 ,  H01L21/0337 ,  H01L21/823821 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/6681 ,  H01L29/66545 ,  H01L29/7851

Abstract: In at least one cell region, a semiconductor device includes fin patterns and at least one overlying gate structure. The fin patterns (dummy and active) are substantially parallel to a first direction. Each gate structure is substantially parallel to a second direction (which is substantially perpendicular to the first direction). First and second active fin patterns have corresponding first and second conductivity types. Each cell region, relative to the second direction, includes: a first active region which includes a sequence of three or more consecutive first active fin patterns located in a central portion of the cell region; a second active region which includes one or more second active fin patterns located between the first active region and a first edge of the cell region; and a third active region which includes one or more second active fin patterns located between the first active region and a second edge of the cell region.

公开(公告)号：US11755813B2

公开(公告)日：2023-09-12

申请号：US17404594

申请日：2021-08-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hui-Zhong Zhuang ,  Ting-Wei Chiang ,  Li-Chun Tien ,  Shun Li Chen ,  Lee-Chung Lu

IPC: G06F30/398 ,  H01L27/02 ,  H01L27/118 ,  G06F30/392

CPC classification number: G06F30/398 ,  G06F30/392 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11881

Abstract: An IC structure includes a first cell and a first and second rail. The first cell includes a first and second active region and a first, a second and a third gate structure. The first active region having a first dopant type. The second active region having a second dopant type. The first gate structure extending in a second direction, overlapping the first or the second active region. The second gate structure extending in the second direction, and overlapping a first edge of the first or second active region. The third gate structure extending in the second direction, and overlapping at least a second edge of the first or second active region. The first rail extending in the first direction and overlapping a middle portion of the first active region. The second rail extending in the first direction and overlapping a middle portion of the second active region.

公开(公告)号：US11562946B2

公开(公告)日：2023-01-24

申请号：US17209878

申请日：2021-03-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC NANJING COMPANY, LIMITED

Inventor： Hidehiro Fujiwara ,  Tze-Chiang Huang ,  Hong-Chen Cheng ,  Yen-Huei Chen ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang ,  Yun-Han Lee ,  Lee-Chung Lu

IPC: G11C11/00 ,  H01L23/48 ,  G11C11/418 ,  H01L21/768 ,  H01L27/11

Abstract: A memory macro structure includes a first memory array, a second memory array, a cell activation circuit coupled to the first and second memory arrays and positioned between the first and second memory arrays, a control circuit coupled to the cell activation circuit and positioned adjacent to the cell activation circuit, and a through-silicon via (TSV) extending through one of the cell activation circuit or the control circuit.

公开(公告)号：US10971586B2

公开(公告)日：2021-04-06

申请号：US16204474

申请日：2018-11-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jung-Chan Yang ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Lee-Chung Lu ,  Li-Chun Tien

IPC: H01L29/06 ,  H01L27/092 ,  H01L27/02 ,  H01L21/033 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  G06F30/392

Abstract: In at least one cell region, a semiconductor device includes fins and at least one overlying gate structure. The fins (dummy and active) are substantially parallel to a first direction. Each gate structure is substantially parallel to a second direction (which is substantially perpendicular to the first direction). First and second active fins have corresponding first and second conductivity types. Each cell region, relative to the second direction, includes: a first active region which includes a sequence of three or more consecutive first active fins located in a central portion of the cell region; a second active region which includes one or more second active fins located between the first active region and a first edge of the cell region; and a third active region which includes one or more second active fins located between the first active region and a second edge of the cell region.

公开(公告)号：US10970450B2

公开(公告)日：2021-04-06

申请号：US15782232

申请日：2017-10-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Fong-Yuan Chang ,  Jyun-Hao Chang ,  Sheng-Hsiung Chen ,  Ho Che Yu ,  Lee-Chung Lu ,  Ni-Wan Fan ,  Po-Hsiang Huang ,  Chi-Yu Lu ,  Jeo-Yen Lee

IPC: G06F30/392 ,  H01L27/118 ,  G06F30/398 ,  G06F30/39 ,  H01L23/538 ,  H01L27/02

Abstract: A semiconductor device comprising active areas and a structure. The active areas are formed as predetermined shapes on a substrate and arranged relative to a grid having first and second tracks which are substantially parallel to corresponding orthogonal first and second directions; The active areas are organized into instances of a first row having a first conductivity and a second row having a second conductivity. Each instance of the first row and of the second row includes a corresponding first and second number predetermined number of the first tracks. The structure has at least two contiguous rows including: at least one instance of the first row; and at least one instance of the second row. In the first direction, the instance(s) of the first row have a first width and the instance(s) of the second row a second width substantially different than the first width.

公开(公告)号：US10664565B2

公开(公告)日：2020-05-26

申请号：US15936712

申请日：2018-03-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chi-Lin Liu ,  Sheng-Hsiung Chen ,  Jerry Chang-Jui Kao ,  Fong-Yuan Chang ,  Lee-Chung Lu ,  Shang-Chih Hsieh ,  Wei-Hsiang Ma

IPC: G06F17/50

Abstract: A method (of expanding a set of standard cells which comprise a library, the library being stored on a non-transitory computer-readable medium) includes: selecting one ad hoc group amongst ad hoc groups of elementary standard cells which are recurrent resulting in a selected group such that the elementary standard cells in the selected group having connections so as to represent a corresponding logic circuit, each elementary standard cell representing a logic gate, and the selected group corresponding providing a selected logical function which is representable correspondingly as a selected Boolean expression; generating, in correspondence to the selected group, one or more macro standard cells; and adding the one or more macro standard cells to, and thereby expanding, the set of standard cells; and wherein at least one aspect of the method is executed by a processor of a computer.

公开(公告)号：US10380315B2

公开(公告)日：2019-08-13

申请号：US15682885

申请日：2017-08-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hui-Zhong Zhuang ,  Ting-Wei Chiang ,  Lee-Chung Lu ,  Li-Chun Tien ,  Shun Li Chen

IPC: G06F17/50 ,  H01L27/02 ,  H01L27/118

Abstract: An IC structure includes a cell, a first rail and a second rail. The cell includes a first and a second active region and a first gate structure. The first and second active region extend in a first direction and is located at a first level. The second active region is separated from the first active region in a second direction. The first gate structure extends in the second direction, overlaps the first and second active region, and is located at a second level. The first rail extends in the first direction, overlaps the first active region, is configured to supply a first supply voltage, and is located at a third level. The second rail extends in the first direction, overlaps the second active region, is located at the third level, separated from the first rail in the second direction, and is configured to supply a second supply voltage.

公开(公告)号：US09747402B2

公开(公告)日：2017-08-29

申请号：US14564934

申请日：2014-12-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Huang-Yu Chen ,  Yuan-Te Hou ,  Fung Song Lee ,  Wen-Ju Yang ,  Gwan Sin Chang ,  Yi-Kan Cheng ,  Li-Chun Tien ,  Lee-Chung Lu

IPC: H01L27/02 ,  G06F17/50 ,  H01L23/528 ,  H01L27/118

CPC classification number: G06F17/5072 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells.