Invention Grant
- Patent Title: Methods for double-patterning-compliant standard cell design
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Application No.: US14564934Application Date: 2014-12-09
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Publication No.: US09747402B2Publication Date: 2017-08-29
- Inventor: Huang-Yu Chen , Yuan-Te Hou , Fung Song Lee , Wen-Ju Yang , Gwan Sin Chang , Yi-Kan Cheng , Li-Chun Tien , Lee-Chung Lu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L27/02
- IPC: H01L27/02 ; G06F17/50 ; H01L23/528 ; H01L27/118
Abstract:
A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells.
Public/Granted literature
- US20150095870A1 Methods for Double-Patterning-Compliant Standard Cell Design Public/Granted day:2015-04-02
Information query
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