公开(公告)号：US11854964B2

公开(公告)日：2023-12-26

申请号：US17459135

申请日：2021-08-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Da Cheng ,  Wei-Hung Lin ,  Hui-Min Huang ,  Chang-Jung Hsueh ,  Po-Hao Tsai ,  Yung-Sheng Lin

IPC: H01L23/26 ,  H01L23/522 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/5226 ,  H01L21/486 ,  H01L24/14

Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device structure includes an interconnection structure over a semiconductor substrate. The semiconductor device structure includes a conductive pillar over the interconnection structure. The conductive pillar has a protruding portion extending towards the semiconductor substrate. The semiconductor device structure includes an upper conductive via between the conductive pillar and the interconnection structure. A center of the upper conductive via is laterally separated from a center of the protruding portion by a first distance. The semiconductor device structure includes a lower conductive via between the upper conductive via and the interconnection structure. The lower conductive via is electrically connected to the conductive pillar through the upper conductive via. A center of the lower conductive via is laterally separated from the center of the protruding portion by a second distance that is shorter than the first distance.

公开(公告)号：US20230062370A1

公开(公告)日：2023-03-02

申请号：US17460347

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wei-Hung Lin ,  Hui-Min Huang ,  Chang-Jung Hsueh ,  Wan-Yu Chiang ,  Ming-Da Cheng ,  Mirng-Ji Lii

IPC: H01L25/18 ,  H01L23/00 ,  H01L21/78 ,  H01L23/31 ,  H01L23/498

Abstract: Provided are a package structure and a method of forming the same. The method includes providing a first package having a plurality of first dies and a plurality of second dies therein; performing a first sawing process to cut the first package into a plurality of second packages, wherein one of the plurality of second packages comprises three first dies and one second die; and performing a second sawing process to remove the second die of the one of the plurality of second packages, so that a cut second package is formed into a polygonal structure with the number of nodes greater than or equal to 5.

公开(公告)号：US11387171B2

公开(公告)日：2022-07-12

申请号：US15997378

申请日：2018-06-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hui-Min Huang ,  Shou-Cheng Hu ,  Chih-Wei Lin ,  Ming-Da Cheng ,  Chung-Shi Liu ,  Chen-Shien Chen

IPC: H01L21/00 ,  H01L23/495 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L25/10

Abstract: A method of packaging a semiconductor die includes connecting an interposer frame directly to a substrate, wherein the interposer frame has a plurality of conductive columns. The method further includes attaching the semiconductor die to the substrate in an opening of the interposer frame, wherein the semiconductor die directly contacts the substrate. The method further includes forming a molding compound to fill space between the semiconductor die and the interposer frame. The method further includes removing a portion of the molding compound to expose the plurality of conductive columns. The method further includes forming a redistribution layer directly contacting a top surface of the semiconductor die and a top surface of the interposer frame.

公开(公告)号：US10861827B2

公开(公告)日：2020-12-08

申请号：US16397479

申请日：2019-04-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Meng-Tse Chen ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Hui-Min Huang ,  Hsuan-Ting Kuo ,  Ming-Da Cheng

IPC: H01L23/02 ,  H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L21/768 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

Abstract: An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first redistribution layer over and coupled to the first die, the first redistribution layer including one or more metal layers disposed in one or more dielectric layers, adhering a second die over the redistribution layer, laminating a first dielectric material over the second die and the first redistribution layer, forming first vias through the first dielectric material to the second die and forming second vias through the first dielectric material to the first redistribution layer, and forming a second redistribution layer over the first dielectric material and over and coupled to the first vias and the second vias.

公开(公告)号：US10510719B2

公开(公告)日：2019-12-17

申请号：US16055294

申请日：2018-08-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu ,  Chung-Shi Liu ,  Meng-Tse Chen ,  Hui-Min Huang ,  Chih-Fan Huang ,  Ming-Da Cheng

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L21/3105 ,  H01L21/683 ,  H01L21/768 ,  H01L21/78 ,  H01L23/528 ,  H01L23/58 ,  H01L25/00 ,  H01L21/56 ,  H01L23/15

Abstract: Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming a dam structure on dies proximate edge regions of the dies. A molding material is disposed around the dies, and a top portion of the molding material and a top portion of the dam structure are removed.

公开(公告)号：US10163804B2

公开(公告)日：2018-12-25

申请号：US15887815

申请日：2018-02-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu ,  Chung-Shi Liu ,  Chih-Fan Huang ,  Hui-Min Huang ,  Wei-Hung Lin ,  Ming-Da Cheng

IPC: H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/10 ,  H01L23/29

Abstract: A method in which microelectronic devices are attached to a substrate surface, wherein spaces interpose neighboring ones of the microelectronic devices. Each microelectronic device has an outermost surface that is substantially parallel to the substrate surface. The substrate is closed in a transfer molding cavity of a transfer molding apparatus such that an internal surface of the transfer molding cavity contacts a substantial portion of each of the outermost surfaces of the microelectronic devices. A molding compound is subsequently injected into the transfer molding cavity, including into the spaces between ones of the plurality of microelectronic devices.

公开(公告)号：US20180108637A1

公开(公告)日：2018-04-19

申请号：US15843507

申请日：2017-12-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu ,  Chung-Shi Liu ,  Meng-Tse Chen ,  Hui-Min Huang ,  Chih-Fan Huang ,  Ming-Da Cheng

IPC: H01L25/065 ,  H01L21/3105

CPC classification number: H01L25/0655 ,  H01L21/31053 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/768 ,  H01L21/78 ,  H01L23/15 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49894 ,  H01L23/528 ,  H01L23/5389 ,  H01L23/564 ,  H01L23/585 ,  H01L24/02 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/0231 ,  H01L2224/02379 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/18162

Abstract: Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming a dam structure on dies proximate edge regions of the dies. A molding material is disposed around the dies, and a top portion of the molding material and a top portion of the dam structure are removed.

公开(公告)号：US09892962B2

公开(公告)日：2018-02-13

申请号：US14953783

申请日：2015-11-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheng-Tar Wu ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Hui-Min Huang ,  Chun-Cheng Lin ,  Ming-Da Cheng

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/00

CPC classification number: H01L21/76834 ,  H01L21/56 ,  H01L21/76828 ,  H01L23/291 ,  H01L23/295 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/5328 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/02313 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05164 ,  H01L2224/05181 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/10125 ,  H01L2224/10126 ,  H01L2224/11462 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13184 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A method of forming a wafer level chip scale package interconnect may include: forming a post-passivation interconnect (PPI) layer over a substrate; forming an interconnect over the PPI layer; and releasing a molding compound material over the substrate, the molding compound material flowing to laterally encapsulate a portion of the interconnect.

公开(公告)号：US09887162B2

公开(公告)日：2018-02-06

申请号：US14225218

申请日：2014-03-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu ,  Chung-Shi Liu ,  Chih-Fan Huang ,  Hui-Min Huang ,  Wei-Hung Lin ,  Ming-Da Cheng

IPC: H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/10 ,  H01L23/29

CPC classification number: H01L23/5389 ,  H01L21/565 ,  H01L21/566 ,  H01L23/295 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method in which microelectronic devices are attached to a substrate surface, wherein spaces interpose neighboring ones of the microelectronic devices. Each microelectronic device has an outermost surface that is substantially parallel to the substrate surface. The substrate is closed in a transfer molding cavity of a transfer molding apparatus such that an internal surface of the transfer molding cavity contacts a substantial portion of each of the outermost surfaces of the microelectronic devices. A molding compound is subsequently injected into the transfer molding cavity, including into the spaces between ones of the plurality of microelectronic devices.

公开(公告)号：US09871018B2

公开(公告)日：2018-01-16

申请号：US15062757

申请日：2016-03-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu ,  Chung-Shi Liu ,  Chih-Fan Huang ,  Hui-Min Huang ,  Wei-Hung Lin ,  Ming-Da Cheng

IPC: H01L25/065 ,  H01L25/10 ,  H01L21/56 ,  H01L21/78 ,  H01L23/538 ,  H01L23/00 ,  H01L21/683 ,  H01L23/04 ,  H01L23/29 ,  H01L23/31 ,  H01L23/367 ,  H01L23/528 ,  H01L23/498

CPC classification number: H01L25/0652 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/04 ,  H01L23/293 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/528 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/17 ,  H01L24/19 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/1302 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82 ,  H01L2224/92125 ,  H01L2224/9222 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00012 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00

Abstract: Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming a mask coating over a carrier, coupling an integrated circuit die over the mask coating, and disposing a molding compound around the integrated circuit die. The method includes forming an interconnect structure over the integrated circuit die and the molding compound.