公开(公告)号：US11289418B2

公开(公告)日：2022-03-29

申请号：US16882521

申请日：2020-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Ling Hwang ,  Chun-Lin Lu ,  Kai-Chiang Wu

IPC: H01L23/522 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/66

Abstract: A package structure includes a redistribution circuit structure, at least one semiconductor die, an insulating encapsulation, insulators, and metallic patterns. The at least one semiconductor die is located on and electrically connected to the redistribution circuit structure. The insulating encapsulation encapsulates the at least one semiconductor die and located on the redistribution circuit structure. The insulators are located on the redistribution circuit structure, wherein the insulators are separated and spaced apart from each other, wherein edges of each of the insulators are distant from edges of the at least one semiconductor die by an offset in a stacking direction of the redistribution circuit structure and the insulating encapsulation. Each of the metallic patterns is located on a respective one of the insulators.

公开(公告)号：US20190355694A1

公开(公告)日：2019-11-21

申请号：US16524146

申请日：2019-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Albert Wan ,  Ching-Hua Hsieh ,  Chung-Hao Tsai ,  Chuei-Tang Wang ,  Chao-Wen Shih ,  Han-Ping Pu ,  Chien-Ling Hwang ,  Pei-Hsuan Lee ,  Tzu-Chun Tang ,  Yu-Ting Chiu ,  Jui-Chang Kuo

IPC: H01L23/00 ,  H01L23/66 ,  H01L21/768 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L25/065 ,  H01L21/56 ,  H01L25/00

Abstract: A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A dielectric layer having a core layer formed thereon is provided. The core layer includes a plurality of cavities penetrating through the core layer. The dielectric layer and the core layer are attached onto the package array such that the core layer is located between the dielectric layer and the package array. A plurality of first conductive patches is formed on the dielectric layer above the cavities.

公开(公告)号：US20190304901A1

公开(公告)日：2019-10-03

申请号：US15939292

申请日：2018-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Ling Hwang ,  Chun-Lin Lu ,  Kai-Chiang Wu

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/66 ,  H01L21/48 ,  H01L21/56

Abstract: A package structure includes a redistribution circuit structure, at least one semiconductor die, an insulating encapsulation, insulators, and metallic patterns. The at least one semiconductor die is located on and electrically connected to the redistribution circuit structure. The insulating encapsulation encapsulates the at least one semiconductor die and located on the redistribution circuit structure. The insulators are located on the redistribution circuit structure, wherein the insulators are separated and spaced apart from each other, wherein edges of each of the insulators are distant from edges of the at least one semiconductor die by an offset in a stacking direction of the redistribution circuit structure and the insulating encapsulation. Each of the metallic patterns is located on a respective one of the insulators.

公开(公告)号：US20190067220A1

公开(公告)日：2019-02-28

申请号：US15690287

申请日：2017-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Albert Wan ,  Chung-Shi Liu ,  Chao-Wen Shih ,  Han-Ping Pu ,  Chien-Ling Hwang

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/683 ,  H01L23/48

Abstract: A package structure in accordance with some embodiments may include an RFIC chip, a redistribution circuit structure, a backside redistribution circuit structure, an isolation film, a die attach film, and an insulating encapsulation. The redistribution circuit structure and the backside redistribution circuit structure are disposed at two opposite sides of the RFIC chip and electrically connected to the RFIC chip. The isolation film is disposed between the backside redistribution circuit structure and the RFIC chip. The die attach film is disposed between the RFIC chip and the isolation film. The insulating encapsulation encapsulates the RFIC chip and the isolation film between the redistribution circuit structure and the backside redistribution circuit structure. The isolation film may have a coefficient of thermal expansion lower than the insulating encapsulation and the die attach film.

公开(公告)号：US09870997B2

公开(公告)日：2018-01-16

申请号：US15270008

申请日：2016-09-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hao Chang ,  Hsin-Hung Liao ,  Hao-Yi Tsai ,  Chien-Ling Hwang ,  Wei-Sen Chang ,  Tsung-Hsien Chiang ,  Tin-Hao Kuo

IPC: H01L21/44 ,  H01L23/538 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76885 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/15313 ,  H01L2924/18162 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2924/00014

Abstract: A method for fabricating an integrated fan-out package is provided. The method includes the following steps. A plurality of conductive posts are placed in apertures of a substrate. A carrier having an adhesive thereon is provided. The conductive posts are transferred to the carrier in a standing orientation by adhering the conductive posts in the apertures to the adhesive. An integrated circuit component is mounted onto the adhesive having the conductive posts adhered thereon. An insulating encapsulation is formed to encapsulate the integrated circuit component and the conductive posts. A redistribution circuit structure is formed on the insulating encapsulation, the integrated circuit component, and the conductive posts, wherein the redistribution circuit structure is electrically connected to the integrated circuit component and the conductive posts. The carrier is removed. At least parts of the adhesive are removed (e.g. patterned or entirely removed) to expose surfaces of the conductive posts. A plurality of conductive terminals are formed on the surfaces of the conductive posts exposed by the openings.

公开(公告)号：US11233032B2

公开(公告)日：2022-01-25

申请号：US16703095

申请日：2019-12-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yeong-Jyh Lin ,  Hsin-Hung Liao ,  Chien-Ling Hwang ,  Bor-Ping Jang ,  Hsiao-Chung Liang ,  Chung-Shi Liu

IPC: H01L23/00 ,  H01L21/48 ,  H01L25/065 ,  H01L25/10 ,  H01L25/00 ,  H01L23/498 ,  H01L25/11 ,  H01L25/03

Abstract: Embodiments of mechanisms for forming a package are provided. The package includes a substrate and a contact pad formed on the substrate. The package also includes a conductive pillar bonded to the contact pad through solder formed between the conductive pillar and the contact pad. The solder is in direct contact with the conductive pillar.

公开(公告)号：US11094561B2

公开(公告)日：2021-08-17

申请号：US16896039

申请日：2020-06-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chien-Ling Hwang ,  Bor-Ping Jang ,  Chung-Shi Liu ,  Hsin-Hung Liao ,  Ying-Jui Huang

IPC: H01L21/56 ,  H01L23/482 ,  H01L23/31 ,  H01L21/48 ,  H01L23/498 ,  H01L21/60 ,  H01L21/603 ,  H01L23/538

Abstract: A semiconductor package structure includes a molding compound, a micro pin extending through the molding compound, and a die surrounded by the molding compound. The micro pin has a top surface, a bottom surface, and a sidewall extending from the bottom surface to the top surface of the micro pin. The sidewall of the micro pin has a first portion and a second portion. The first portion of the sidewall is adjacent to the bottom surface of the micro pin and free of the molding compound. The second portion of the sidewall is adjacent to the top surface of the micro pin and in contact with the molding compound.

公开(公告)号：US10679866B2

公开(公告)日：2020-06-09

申请号：US14622484

申请日：2015-02-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chien-Ling Hwang ,  Bor-Ping Jang ,  Chung-Shi Liu ,  Hsin-Hung Liao ,  Ying-Jui Huang

IPC: H01L21/56 ,  H01L23/482 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/60 ,  H01L21/603 ,  H01L23/538

Abstract: A semiconductor package includes a carrier, at least and adhesive portion, a plurality of micro pins and a die. The carrier has a first surface and second surface opposite to the first surface. The adhesive portion is disposed on the first surface, and the plurality of the micro pins is disposed in the adhesive portions. The die is disposed on the remaining adhesive portion free of the micro pins.

公开(公告)号：US11631652B2

公开(公告)日：2023-04-18

申请号：US16663362

申请日：2019-10-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Jui Huang ,  Ching-Hua Hsieh ,  Chien-Ling Hwang ,  Chia-Sheng Huang

IPC: H01L23/00 ,  H01L21/67 ,  H01L21/68 ,  H01L21/82

Abstract: A method and an apparatus for bonding semiconductor substrates are provided. The method includes at least the following steps. A first position of a first semiconductor substrate on a first support is gauged by a gauging component embedded in the first support and a first sensor facing towards the gauging component. A second semiconductor substrate is transferred to a position above the first semiconductor substrate by a second support. A second position of the second semiconductor substrate is gauged by a second sensor mounted on the second support and located above the first support. The first semiconductor substrate is positioned based on the second position of the second semiconductor substrate. The second semiconductor substrate is bonded to the first semiconductor substrate.

公开(公告)号：US20200335477A1

公开(公告)日：2020-10-22

申请号：US16923115

申请日：2020-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Albert Wan ,  Ching-Hua Hsieh ,  Chung-Hao Tsai ,  Chuei-Tang Wang ,  Chao-Wen Shih ,  Han-Ping Pu ,  Chien-Ling Hwang ,  Pei-Hsuan Lee ,  Tzu-Chun Tang ,  Yu-Ting Chiu ,  Jui-Chang Kuo

IPC: H01L23/00 ,  H01L23/538 ,  H01L21/768 ,  H01L21/48 ,  H01L23/66 ,  H01L25/00 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L21/683

Abstract: A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A core layer and a dielectric layer are sequentially stacked over the package array. The core layer includes a plurality of cavities. A plurality of first conductive patches is formed on the dielectric layer above the cavities.