公开(公告)号：US20080151651A1

公开(公告)日：2008-06-26

申请号：US11836283

申请日：2007-08-09

申请人： Sang-yun Kim ,  Jung-bae Lee ,  Young-don Choi

发明人： Sang-yun Kim ,  Jung-bae Lee ,  Young-don Choi

IPC分类号： G11C7/00

CPC分类号： G11C7/1006

摘要： A semiconductor memory device utilizing a data coding method in an initial operation. The semiconductor memory device includes a plurality of counters communicating with a data coding unit. The counters count the number of data bits and flag information data bits in a first logic state in a first data group which includes at least one data bit and second through nth groups each including at least one data bit and flag information. The data coding unit selectively applies a first operation mode and a second operation mode to each of the first through nth data groups and codes the data of each of the first through nth data groups. The first operation mode codes the data of each of the first through nth data groups such that the counted number of data bits in the first logic state in each of the first through nth groups is minimized. The second operation mode codes the data of each of the first through nth groups such that the difference between the number of data bits and flag information data bits in the first logic state and the number of data bits and flag information data bits in a second logic state in the first through nth data groups is minimized. In this manner, the semiconductor memory device and the associated data coding method prevents the initial logic state of data from being changed due to a voltage drop in the initial operation of the device.

摘要翻译： 一种在初始操作中利用数据编码方法的半导体存储器件。 半导体存储器件包括与数据编码单元通信的多个计数器。 计数器在包括至少一个数据位和第二至第n组的第一数据组中对第一逻辑状态中的数据位和标志信息数据位的数目进行计数，每个包括至少一个数据位和标志信息。 数据编码单元选择性地对第一至第n数据组中的每一个应用第一操作模式和第二操作模式，并对第一至第n数据组中的每一个的数据进行编码。 第一操作模式对第一至第n数据组中的每一个的数据进行编码，使得第一至第n组中的每一个中的第一逻辑状态中的数据位的计数数量最小化。 第二操作模式对第一至第n组中的每一个的数据进行编码，使得第一逻辑状态中的数据位数和标志信息数据位之间的差异以及第二逻辑中的数据位和标志信息数据位的数量 在第一至第n个数据组中的状态被最小化。 以这种方式，半导体存储器件和相关联的数据编码方法防止数据的初始逻辑状态由于器件的初始操作中的电压降而被改变。

公开(公告)号：US07551514B2

公开(公告)日：2009-06-23

申请号：US11836283

申请日：2007-08-09

申请人： Sang-yun Kim ,  Jung-bae Lee ,  Young-don Choi

发明人： Sang-yun Kim ,  Jung-bae Lee ,  Young-don Choi

IPC分类号： G11C8/00

CPC分类号： G11C7/1006

摘要： A semiconductor memory device utilizing a data coding method in an initial operation. The device includes a plurality of counters that count the number of data bits and flag information data bits. A data coding unit selectively applies a first and second operation mode. The first operation mode codes the data of the first through nth data groups such that the counted number of data bits in a first logic state is minimized. The second operation mode codes the data of the first through nth data groups such that the difference between the number of data bits and flag information bits in the first and second logic state are minimized. This prevents the initial logic state of data from being changed due to a voltage drop in the initial operation of the device.

摘要翻译： 一种在初始操作中利用数据编码方法的半导体存储器件。 该装置包括对数据位数和标志信息数据位进行计数的多个计数器。 数据编码单元选择性地应用第一和第二操作模式。 第一操作模式对第一至第n数据组的数据进行编码，使得在第一逻辑状态中的计数的数据位数最小化。 第二操作模式对第一至第n数据组的数据进行编码，使得第一和第二逻辑状态中的数据位数和标志信息位之间的差最小化。 这样可防止数据的初始逻辑状态由于器件的初始操作中的电压降而被改变。

公开(公告)号：US08482951B2

公开(公告)日：2013-07-09

申请号：US13023738

申请日：2011-02-09

申请人： Chul-woo Yi ,  Seong-jin Jang ,  Jin-seok Kwak ,  Tai-young Ko ,  Joung-yeal Kim ,  Sang-yun Kim ,  Sang-kyun Park ,  Jung-bae Lee

发明人： Chul-woo Yi ,  Seong-jin Jang ,  Jin-seok Kwak ,  Tai-young Ko ,  Joung-yeal Kim ,  Sang-yun Kim ,  Sang-kyun Park ,  Jung-bae Lee

IPC分类号： G11C5/02

CPC分类号： G11C5/063 ,  G11C7/062 ,  G11C7/065 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10885 ,  H01L27/10897 ,  Y10T29/41

摘要： A semiconductor memory device having an open bitline memory structure from which an edge dummy memory block is removed, the semiconductor memory device includes a memory block, an edge sense amplification block including a first sense amplifier having a first bitline, a first complementary bitline, and a first amplification circuit comprising a first transistor having a first size, a central sense amplification block including a second sense amplifier having a second bitline, a second complementary bitline, and a second amplification circuit comprising a second transistor having a second size different from the first size, a capacitor block electrically connected to the edge sense amplification block.

摘要翻译： 一种具有开放位线存储器结构的半导体存储器件，其中除去边缘伪存储器块，所述半导体存储器件包括存储器块，边沿读出放大块，其包括第一读出放大器，所述第一读出放大器具有第一位线，第一互补位线和 第一放大电路，包括具有第一尺寸的第一晶体管，中央读出放大块，包括具有第二位线的第二读出放大器，第二互补位线和第二放大电路，所述第二放大电路包括第二晶体管， 电容器块电连接到边缘检测放大块。

公开(公告)号：US08891324B2

公开(公告)日：2014-11-18

申请号：US13915338

申请日：2013-06-11

申请人： Chul-woo Yi ,  Seong-jin Jang ,  Jin-seok Kwak ,  Tai-young Ko ,  Joung-yeal Kim ,  Sang-yun Kim ,  Sang-kyun Park ,  Jung-bae Lee

发明人： Chul-woo Yi ,  Seong-jin Jang ,  Jin-seok Kwak ,  Tai-young Ko ,  Joung-yeal Kim ,  Sang-yun Kim ,  Sang-kyun Park ,  Jung-bae Lee

IPC分类号： G11C7/00 ,  G11C5/06 ,  G11C7/06 ,  H01L27/02 ,  H01L27/105 ,  G11C7/18 ,  G11C11/4091 ,  H01L27/108

CPC分类号： G11C5/063 ,  G11C7/062 ,  G11C7/065 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10885 ,  H01L27/10897 ,  Y10T29/41

摘要： A semiconductor memory device having an open bitline memory structure from which an edge dummy memory block is removed, the semiconductor memory device includes a memory block, an edge sense amplification block including a first sense amplifier having a first bitline, a first complementary bitline, and a first amplification circuit comprising a first transistor having a first size, a central sense amplification block including a second sense amplifier having a second bitline, a second complementary bitline, and a second amplification circuit comprising a second transistor having a second size different from the first size, a capacitor block electrically connected to the edge sense amplification block.

摘要翻译： 一种具有开放位线存储器结构的半导体存储器件，其中除去边缘伪存储器块，所述半导体存储器件包括存储器块，边沿读出放大块，其包括第一读出放大器，所述第一读出放大器具有第一位线，第一互补位线和 第一放大电路，包括具有第一尺寸的第一晶体管，中央读出放大块，包括具有第二位线的第二读出放大器，第二互补位线和第二放大电路，所述第二放大电路包括第二晶体管， 电容器块电连接到边缘检测放大块。

公开(公告)号：US08446988B2

公开(公告)日：2013-05-21

申请号：US13280456

申请日：2011-10-25

申请人： Hoe-ju Chung ,  Jung-bae Lee

发明人： Hoe-ju Chung ,  Jung-bae Lee

IPC分类号： H04L27/06

CPC分类号： H04L25/0264 ,  H04L25/0272

摘要： In a communication system, data is selectively transmitted using single-ended or differential signaling. The data is transmitted in relation to a plurality of clock signals having different relative phases. When the data is transmitted using single-ended signaling, data on adjacent signal lines undergo logic transitions at different times in relation to the plurality of clock signals.

摘要翻译： 在通信系统中，使用单端或差分信令有选择地发送数据。 相对于具有不同相对相位的多个时钟信号发送数据。 当使用单端信令发送数据时，相邻信号线上的数据相对于多个时钟信号在不同时刻进行逻辑转换。

公开(公告)号：US20130016574A1

公开(公告)日：2013-01-17

申请号：US13548484

申请日：2012-07-13

申请人： Jung-sik Kim ,  Cheol Kim ,  Sang-ho Shin ,  Jung-bae Lee ,  Chan-yong Lee ,  Sung-min Yim ,  Tae-seong Jang ,  Joo-sun Choi

发明人： Jung-sik Kim ,  Cheol Kim ,  Sang-ho Shin ,  Jung-bae Lee ,  Chan-yong Lee ,  Sung-min Yim ,  Tae-seong Jang ,  Joo-sun Choi

IPC分类号： G11C29/08 ,  G11C7/00

CPC分类号： G11C29/50016 ,  G11C5/04 ,  G11C11/40 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40622 ,  G11C2211/4061 ,  G11C2211/4065

摘要： A semiconductor memory device having improved refresh characteristics includes a memory array including a plurality of memory cells; a test unit configured to test refresh characteristics of the memory array and generate a first fail address signal; a storage unit configured to store the first fail address signal; and a refresh unit configured to perform a refresh operation on the memory array, wherein the refresh unit is configured to receive the first fail address signal from the storage unit, perform the refresh operation on a first memory cell that does not correspond to the first fail address signal according to a first period, and perform the refresh operation on a second memory cell that corresponds to the first fail address signal according to a second period that is shorter than the first period.

摘要翻译： 具有改进的刷新特性的半导体存储器件包括包括多个存储器单元的存储器阵列; 测试单元，被配置为测试所述存储器阵列的刷新特性并产生第一故障地址信号; 存储单元，被配置为存储所述第一失败地址信号; 以及刷新单元，被配置为对所述存储器阵列执行刷新操作，其中所述刷新单元被配置为从所述存储单元接收所述第一故障地址信号，对与所述第一故障不对应的第一存储器单元执行刷新操作 根据第一期间的地址信号，根据比第一期间短的第二期间对与第一失败地址信号对应的第二存储单元进行刷新动作。

公开(公告)号：US07957217B2

公开(公告)日：2011-06-07

申请号：US12266716

申请日：2008-11-07

申请人： Moon-sook Park ,  Hoe-ju Chung ,  Jung-bae Lee

发明人： Moon-sook Park ,  Hoe-ju Chung ,  Jung-bae Lee

IPC分类号： G11C8/00

CPC分类号： G11C5/147 ,  G11C5/04

摘要： The invention relates generally to a multi-chip package (MCP) memory device, and more particularly, but without limitation, to a MCP memory device having a reduced size. In one embodiment, the MCP memory device includes: a transfer memory chip; and a plurality of memory chips coupled to the transfer memory chip, each of the plurality of memory chips including an internal voltage generating circuit, the transfer memory chip configured to receive a plurality of command signals from outside the MCP memory device, the transfer memory chip further configured to output a plurality of control signals to the plurality of memory chips based on the plurality of command signals. Embodiments of the invention also relate to a method of controlling an internal voltage of the MCP memory device.

摘要翻译： 本发明一般涉及一种多芯片封装（MCP）存储器件，尤其涉及但不限于具有减小尺寸的MCP存储器件。 在一个实施例中，MCP存储器件包括：传送存储器芯片; 以及多个存储器芯片，其耦合到所述传送存储器芯片，所述多个存储器芯片中的每一个包括内部电压产生电路，所述传送存储器芯片被配置为从所述MCP存储器设备的外部接收多个命令信号，所述传送存储器芯片 还被配置为基于所述多个命令信号将多个控制信号输出到所述多个存储器芯片。 本发明的实施例还涉及一种控制MCP存储器件的内部电压的方法。

公开(公告)号：US07948272B2

公开(公告)日：2011-05-24

申请号：US10990412

申请日：2004-11-18

申请人： Dong-jin Lee ,  Jung-bae Lee ,  Kyu-hyoun Kim

发明人： Dong-jin Lee ,  Jung-bae Lee ,  Kyu-hyoun Kim

IPC分类号： H03K5/22

CPC分类号： H03K19/003

摘要： An input buffer which detects an input signal. The input buffer including an output node, a first buffer, and a second buffer. The first buffer may control the voltage level of the output node when the voltage level of a reference voltage signal is equal to a predetermined voltage level. The second buffer may control the voltage level of the output node in response to the input signal when the voltage level of the reference voltage signal is lower than the predetermined voltage level. The second buffer may maintain the output node at a first level. The second buffer may include an output control section and a level control unit. The output control section may receive the input signal and generate a level output signal at a second level. The level control section may generate a control signal which maintains the output node at the first level, in response to the level output signal when the voltage level of the reference voltage signal is lower than the predetermined voltage level of the first voltage and may intercept the control signal when the voltage level of the reference voltage signal is equal to the predetermined voltage level.

摘要翻译： 输入缓冲器，用于检测输入信号。 输入缓冲器包括输出节点，第一缓冲器和第二缓冲器。 当参考电压信号的电压电平等于预定电压电平时，第一缓冲器可以控制输出节点的电压电平。 当参考电压信号的电压电平低于预定电压电平时，第二缓冲器可以响应于输入信号来控制输出节点的电压电平。 第二缓冲器可以将输出节点维持在第一级。 第二缓冲器可以包括输出控制部分和电平控制单元。 输出控制部分可以接收输入信号并产生第二电平的电平输出信号。 当参考电压信号的电压电平低于第一电压的预定电压电平时，电平控制部分可以响应于电平输出信号而产生将输出节点维持在第一电平的控制信号，并且可以拦截 当参考电压信号的电压电平等于预定电压电平时，控制信号。

公开(公告)号：US20080205113A1

公开(公告)日：2008-08-28

申请号：US12071745

申请日：2008-02-26

申请人： UK-song Kang ,  Jung-bae Lee

发明人： UK-song Kang ,  Jung-bae Lee

IPC分类号： G11C5/06

CPC分类号： G11C5/025 ,  G11C5/04

摘要： A multi memory chip stacked on a multi core CPU includes a plurality of memories, each memory corresponding to a CPU core from among the CPU cores and being configured to directly transmit data between the other memories of the multi memory chip.

摘要翻译： 堆叠在多核CPU上的多存储器芯片包括多个存储器，每个存储器对应于CPU核心中的CPU核心，并且被配置为直接在多存储器芯片的其他存储器之间传输数据。

公开(公告)号：US07236012B2

公开(公告)日：2007-06-26

申请号：US10970016

申请日：2004-10-22

申请人： Geun-hee Cho ,  Jung-bae Lee

发明人： Geun-hee Cho ,  Jung-bae Lee

IPC分类号： H03K19/0175

CPC分类号： G11C7/1051 ,  G11C7/1057

摘要： A data output driver of a semiconductor memory device can minimize a difference in slew rate of an output signal according to a selected bit organization. The data output driver includes a pull-up driver and a pull-down driver. The pull-up driver pulls up an output terminal and the pull-down driver pulls down the output terminal. In particular, current driving capabilities of the pull-up driver and/or the pull-down driver are changed in response to bit organization information signals of the semiconductor memory device.

摘要翻译： 半导体存储器件的数据输出驱动器可以根据所选位组织来最小化输出信号的转换速率差。 数据输出驱动器包括一个上拉驱动器和一个下拉驱动器。 上拉驱动器拉出输出端子，下拉驱动器拉出输出端子。 特别地，上拉驱动器和/或下拉驱动器的当前驱动能力响应于半导体存储器件的位组织信息信号而改变。