公开(公告)号：US09076548B1

公开(公告)日：2015-07-07

申请号：US14056995

申请日：2013-10-18

申请人： Duk-Ha Park ,  Chul-Sung Park ,  Jung-Bae Lee

发明人： Duk-Ha Park ,  Chul-Sung Park ,  Jung-Bae Lee

IPC分类号： G11C7/00 ,  G11C11/402

CPC分类号： G11C5/02 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40615 ,  G11C13/0033 ,  G11C16/3418

摘要： A method of refreshing a semiconductor memory device includes performing a first refresh operation for memory cells included in a memory cell array, and determining whether a command other than a refresh command is applied to the semiconductor memory device in a refresh cycle of the first refresh operation. The method further includes continuing to perform the first refresh operation when a command other the refresh command is applied to the semiconductor memory device in one refresh cycle of the first refresh operation, and performing a second refresh operation when a command other than the refresh command is not applied to the semiconductor memory device in one refresh cycle of the first refresh operation. A refresh time of the second refresh operation is greater than a refresh time of the first refresh operation.

摘要翻译： 一种刷新半导体存储器件的方法包括对包含在存储单元阵列中的存储单元执行第一刷新操作，并且在第一刷新操作的刷新周期中确定除刷新命令之外的命令是否被应用于半导体存储器件 。 该方法还包括当在第一刷新操作的一个刷新周期中将另外刷新命令的命令施加到半导体存储器件的命令时继续执行第一刷新操作，并且当除了刷新命令之外的命令是执行第二刷新操作时 在第一刷新操作的一个刷新周期中不施加到半导体存储器件。 第二刷新操作的刷新时间大于第一刷新操作的刷新时间。

公开(公告)号：US08446988B2

公开(公告)日：2013-05-21

申请号：US13280456

申请日：2011-10-25

申请人： Hoe-ju Chung ,  Jung-bae Lee

发明人： Hoe-ju Chung ,  Jung-bae Lee

IPC分类号： H04L27/06

CPC分类号： H04L25/0264 ,  H04L25/0272

摘要： In a communication system, data is selectively transmitted using single-ended or differential signaling. The data is transmitted in relation to a plurality of clock signals having different relative phases. When the data is transmitted using single-ended signaling, data on adjacent signal lines undergo logic transitions at different times in relation to the plurality of clock signals.

摘要翻译： 在通信系统中，使用单端或差分信令有选择地发送数据。 相对于具有不同相对相位的多个时钟信号发送数据。 当使用单端信令发送数据时，相邻信号线上的数据相对于多个时钟信号在不同时刻进行逻辑转换。

公开(公告)号：US08396682B2

公开(公告)日：2013-03-12

申请号：US12900547

申请日：2010-10-08

申请人： Chi-Sung Oh ,  Dong-Hyuk Lee ,  Ho-Cheol Lee ,  Jang-Woo Ryu ,  Jung-Bae Lee

发明人： Chi-Sung Oh ,  Dong-Hyuk Lee ,  Ho-Cheol Lee ,  Jang-Woo Ryu ,  Jung-Bae Lee

IPC分类号： G01R27/28 ,  G06F19/00

CPC分类号： G01R31/2884 ,  G01R31/31726

摘要： A semiconductor device is provided. The semiconductor device applies data applied through a bump pad on which a bump is mounted through a test pad to a test apparatus such that the reliability of the test can be improved. The amount of test pads is significantly reduced by allowing data output through bump pads to be selectively applied to a test pad. Data and signals applied from test pads are synchronized with each other and applied to bump pads during a test operation such that the reliability of the test can be improved without the need of an additional test chip.

摘要翻译： 提供半导体器件。 半导体器件将通过测试焊盘安装有凸块的凸块焊盘施加的数据施加到测试装置，使得可以提高测试的可靠性。 通过允许通过凸块焊盘的数据输出被选择性地施加到测试焊盘，测试焊盘的量显着减少。 从测试焊盘施加的数据和信号彼此同步，并在测试操作期间应用于凸块焊盘，从而可以提高测试的可靠性，而无需额外的测试芯片。

公开(公告)号：US08379477B2

公开(公告)日：2013-02-19

申请号：US13019858

申请日：2011-02-02

申请人： Cheol Kim ,  Sang-Kyun Park ,  Jung-Bae Lee ,  Jun-Phyo Lee

发明人： Cheol Kim ,  Sang-Kyun Park ,  Jung-Bae Lee ,  Jun-Phyo Lee

IPC分类号： G11C8/10

CPC分类号： G11C8/14 ,  G11C8/08

摘要： Provided is a semiconductor memory device including a sub-word-line driving circuit capable of reducing an amount of leakage current due to coupling. The semiconductor memory device includes a word-line enable signal generating circuit and a sub-word-line driving circuit. The sub-word-line driving circuit provides a pull-down current path between a selected word line and ground for a pulse type period of time in a precharge mode following an active mode for the selected word line, generates a word line driving signal on the basis of a main word line driving signal, a first sub-word-line control signal, and a second sub-word-line control signal, and provides the word line driving signal to a memory cell array. The semiconductor memory device may reduce an amount of leakage current flowing to a ground through the sub-word-line driving circuit.

摘要翻译： 提供了一种半导体存储器件，其包括能够减少由耦合引起的漏电流量的子字线驱动电路。 半导体存储器件包括字线使能信号发生电路和子字线驱动电路。 子字线驱动电路在所选字线的有效模式之后的预充电模式中的脉冲类型时段期间，在所选字线和地之间提供下拉电流路径，生成字线驱动信号 主字线驱动信号的基础，第一子字线控制信号和第二子字线控制信号，并将字线驱动信号提供给存储单元阵列。 半导体存储器件可以减少通过子字线驱动电路流向地的漏电流量。

公开(公告)号：US20130016574A1

公开(公告)日：2013-01-17

申请号：US13548484

申请日：2012-07-13

申请人： Jung-sik Kim ,  Cheol Kim ,  Sang-ho Shin ,  Jung-bae Lee ,  Chan-yong Lee ,  Sung-min Yim ,  Tae-seong Jang ,  Joo-sun Choi

发明人： Jung-sik Kim ,  Cheol Kim ,  Sang-ho Shin ,  Jung-bae Lee ,  Chan-yong Lee ,  Sung-min Yim ,  Tae-seong Jang ,  Joo-sun Choi

IPC分类号： G11C29/08 ,  G11C7/00

CPC分类号： G11C29/50016 ,  G11C5/04 ,  G11C11/40 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40622 ,  G11C2211/4061 ,  G11C2211/4065

摘要： A semiconductor memory device having improved refresh characteristics includes a memory array including a plurality of memory cells; a test unit configured to test refresh characteristics of the memory array and generate a first fail address signal; a storage unit configured to store the first fail address signal; and a refresh unit configured to perform a refresh operation on the memory array, wherein the refresh unit is configured to receive the first fail address signal from the storage unit, perform the refresh operation on a first memory cell that does not correspond to the first fail address signal according to a first period, and perform the refresh operation on a second memory cell that corresponds to the first fail address signal according to a second period that is shorter than the first period.

摘要翻译： 具有改进的刷新特性的半导体存储器件包括包括多个存储器单元的存储器阵列; 测试单元，被配置为测试所述存储器阵列的刷新特性并产生第一故障地址信号; 存储单元，被配置为存储所述第一失败地址信号; 以及刷新单元，被配置为对所述存储器阵列执行刷新操作，其中所述刷新单元被配置为从所述存储单元接收所述第一故障地址信号，对与所述第一故障不对应的第一存储器单元执行刷新操作 根据第一期间的地址信号，根据比第一期间短的第二期间对与第一失败地址信号对应的第二存储单元进行刷新动作。

公开(公告)号：US20120272112A1

公开(公告)日：2012-10-25

申请号：US13453447

申请日：2012-04-23

申请人： Chi-sung OH ,  Jung-sik KIM ,  Ho-cheol LEE ,  Jung-bae LEE

发明人： Chi-sung OH ,  Jung-sik KIM ,  Ho-cheol LEE ,  Jung-bae LEE

IPC分类号： G01R31/3177 ,  H01L23/485 ,  G06F11/25

CPC分类号： G01R31/318555 ,  G01R31/318538 ,  G01R31/318597 ,  G01R31/3187 ,  H01L22/32 ,  H01L23/481 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13541 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81193 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/206

摘要： Semiconductor devices configured to test connectivity of micro bumps including one or more micro bumps and a boundary scan test block for testing connectivity of the micro bumps by scanning data input to the micro bumps and outputting the scanned data. The semiconductor device may include a first chip including solder balls and at least one or more switches electrically coupled with the respective solder balls, and a second chip stacked on top of the first chip and electrically coupled with the switches in direct access mode, including micro bumps that input/output signals transmitted from/to the solder balls.

摘要翻译： 半导体器件被配置为测试包括一个或多个微凸块的微凸块和边界扫描测试块的连接性，用于通过扫描输入到微凸块的数据并输出扫描数据来测试微凸块的连接性。 半导体器件可以包括第一芯片，其包括焊球和与各个焊球电耦合的至少一个或多个开关，以及堆叠在第一芯片的顶部上并与直流存取模式的开关电耦合的第二芯片，包括微 从焊球传出的输入/输出信号的凸起。

公开(公告)号：US08253478B2

公开(公告)日：2012-08-28

申请号：US12325846

申请日：2008-12-01

申请人： Jin-Kyoung Jung ,  Jung-Bae Lee ,  Kyu-Hyoun Kim

发明人： Jin-Kyoung Jung ,  Jung-Bae Lee ,  Kyu-Hyoun Kim

IPC分类号： G05F1/10

CPC分类号： G05F1/465

摘要： An internal voltage generating circuit is provided. The internal voltage generating circuit of a semiconductor device includes a control signal generating circuit for generating a control signal according to a number of data bits, a comparator for comparing a reference voltage to an internal voltage to generate a driving signal when the control signal is inactivated, a driving signal control circuit for inactivating the driving signal when the control signal is activated, and an internal voltage driving circuit for receiving an external power voltage and generating the internal voltage in response to the driving signal. Therefore, an internal voltage can be turned to a reference voltage level or to an external power voltage level according to the number of data input and/or output bits of a semiconductor device, and even when the number of data input and/or output bits is increased, a data access speed can be improved.

摘要翻译： 提供内部电压产生电路。 半导体器件的内部电压产生电路包括：控制信号发生电路，用于根据多个数据位产生控制信号;比较器，用于将参考电压与内部电压进行比较，以在控制信号失效时产生驱动信号 ，用于当所述控制信号被激活时使所述驱动信号失活的驱动信号控制电路和用于接收外部电源电压并且响应于所述驱动信号产生所述内部电压的内部电压驱动电路。 因此，可以根据半导体器件的数据输入和/或输出位的数量将内部电压转换为参考电压电平或外部电源电压，并且即使当数据输入和/或输出位数 增加，可以提高数据访问速度。

公开(公告)号：US08112680B2

公开(公告)日：2012-02-07

申请号：US12044183

申请日：2008-03-07

申请人： Hoe-Ju Chung ,  Jung-Bae Lee

发明人： Hoe-Ju Chung ,  Jung-Bae Lee

IPC分类号： G06F11/00

CPC分类号： G06F11/1008 ,  G11C5/02 ,  G11C5/04 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1045 ,  G11C2029/0411 ,  H04L1/0041 ,  H04L1/0057

摘要： A system, device and related method are used to communicate data via a plurality of data lanes including a selected data lane. In a first mode of operation, payload data and related supplemental data are communicated via the plurality of data lanes including the selected data lane. In a second mode of operation, only payload data is communicated via the plurality of data lanes, except the selected data lane.

摘要翻译： 系统，设备和相关方法用于经由包括所选择的数据通道的多个数据通道来传送数据。 在第一操作模式中，经由包括所选择的数据通道的多个数据通道来传送有效载荷数据和相关的补充数据。 在第二种操作模式中，只有有效载荷数据经由多个数据通道被传送，除了所选择的数据通道。

公开(公告)号：US20110199808A1

公开(公告)日：2011-08-18

申请号：US13023738

申请日：2011-02-09

申请人： Chul-woo YI ,  Seong-jin JANG ,  Jin-seok KWAK ,  Tai-young KO ,  Joung-yeal KIM ,  Sang-yun KIM ,  Sang-kyun PARK ,  Jung-bae LEE

发明人： Chul-woo YI ,  Seong-jin JANG ,  Jin-seok KWAK ,  Tai-young KO ,  Joung-yeal KIM ,  Sang-yun KIM ,  Sang-kyun PARK ,  Jung-bae LEE

IPC分类号： G11C5/06 ,  G11C5/10 ,  H01L21/02

CPC分类号： G11C5/063 ,  G11C7/062 ,  G11C7/065 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10885 ,  H01L27/10897 ,  Y10T29/41

摘要： A semiconductor memory device having an open bitline memory structure from which an edge dummy memory block is removed, the semiconductor memory device includes a memory block, an edge sense amplification block including a first sense amplifier having a first bitline, a first complementary bitline, and a first amplification circuit comprising a first transistor having a first size, a central sense amplification block including a second sense amplifier having a second bitline, a second complementary bitline, and a second amplification circuit comprising a second transistor having a second size different from the first size, a capacitor block electrically connected to the edge sense amplification block.

摘要翻译： 一种具有开放位线存储器结构的半导体存储器件，其中除去边缘伪存储器块，所述半导体存储器件包括存储器块，边沿读出放大块，其包括第一读出放大器，所述第一读出放大器具有第一位线，第一互补位线和 第一放大电路，包括具有第一尺寸的第一晶体管，中央读出放大块，包括具有第二位线的第二读出放大器，第二互补位线和第二放大电路，所述第二放大电路包括第二晶体管， 电容器块电连接到边缘检测放大块。

公开(公告)号：US07957217B2

公开(公告)日：2011-06-07

申请号：US12266716

申请日：2008-11-07

申请人： Moon-sook Park ,  Hoe-ju Chung ,  Jung-bae Lee

发明人： Moon-sook Park ,  Hoe-ju Chung ,  Jung-bae Lee

IPC分类号： G11C8/00

CPC分类号： G11C5/147 ,  G11C5/04

摘要： The invention relates generally to a multi-chip package (MCP) memory device, and more particularly, but without limitation, to a MCP memory device having a reduced size. In one embodiment, the MCP memory device includes: a transfer memory chip; and a plurality of memory chips coupled to the transfer memory chip, each of the plurality of memory chips including an internal voltage generating circuit, the transfer memory chip configured to receive a plurality of command signals from outside the MCP memory device, the transfer memory chip further configured to output a plurality of control signals to the plurality of memory chips based on the plurality of command signals. Embodiments of the invention also relate to a method of controlling an internal voltage of the MCP memory device.

摘要翻译： 本发明一般涉及一种多芯片封装（MCP）存储器件，尤其涉及但不限于具有减小尺寸的MCP存储器件。 在一个实施例中，MCP存储器件包括：传送存储器芯片; 以及多个存储器芯片，其耦合到所述传送存储器芯片，所述多个存储器芯片中的每一个包括内部电压产生电路，所述传送存储器芯片被配置为从所述MCP存储器设备的外部接收多个命令信号，所述传送存储器芯片 还被配置为基于所述多个命令信号将多个控制信号输出到所述多个存储器芯片。 本发明的实施例还涉及一种控制MCP存储器件的内部电压的方法。