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    METHOD OF CONTROLLING INTERNAL VOLTAGE AND MULTI-CHIP PACKAGE MEMORY PREPARED USING THE SAME
    1.
    发明申请
    METHOD OF CONTROLLING INTERNAL VOLTAGE AND MULTI-CHIP PACKAGE MEMORY PREPARED USING THE SAME 有权
    控制内部电压的方法和使用其制备的多芯片封装内存

    公开(公告)号：US20090125687A1

    公开(公告)日：2009-05-14

    申请号：US12266716

    申请日：2008-11-07

    申请人： Moon-sook PARK ,  Hoe-ju CHUNG ,  Jung-bae LEE

    发明人： Moon-sook PARK ,  Hoe-ju CHUNG ,  Jung-bae LEE

    IPC分类号： G06F12/00

    CPC分类号： G11C5/147 ,  G11C5/04

    摘要： The invention relates generally to a multi-chip package (MCP) memory device, and more particularly, but without limitation, to a MCP memory device having a reduced size. In one embodiment, the MCP memory device includes: a transfer memory chip; and a plurality of memory chips coupled to the transfer memory chip, each of the plurality of memory chips including an internal voltage generating circuit, the transfer memory chip configured to receive a plurality of command signals from outside the MCP memory device, the transfer memory chip further configured to output a plurality of control signals to the plurality of memory chips based on the plurality of command signals. Embodiments of the invention also relate to a method of controlling an internal voltage of the MCP memory device.

    摘要翻译： 本发明一般涉及一种多芯片封装（MCP）存储器件，尤其涉及但不限于具有减小尺寸的MCP存储器件。 在一个实施例中，MCP存储器件包括：传送存储器芯片; 以及多个存储器芯片，其耦合到所述传送存储器芯片，所述多个存储器芯片中的每一个包括内部电压产生电路，所述传送存储器芯片被配置为从所述MCP存储器设备的外部接收多个命令信号，所述传送存储器芯片 还被配置为基于所述多个命令信号将多个控制信号输出到所述多个存储器芯片。 本发明的实施例还涉及一种控制MCP存储器件的内部电压的方法。

    Charge pump circuit and method thereof
    2.
    发明申请
    Charge pump circuit and method thereof 审中-公开
    电荷泵电路及其方法

    公开(公告)号：US20070109032A1

    公开(公告)日：2007-05-17

    申请号：US11598047

    申请日：2006-11-13

    申请人： Moon-Sook Park ,  Kyu-Hyoun Kim

    发明人： Moon-Sook Park ,  Kyu-Hyoun Kim

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0896 ,  H03L7/0812

    摘要： A charge pump circuit and method thereof are provided. The example charge pump may include a first switch transistor supplying a first current to an output node in response to a first signal to increase a level of current at the output node, a second switch transistor sinking a second current from the output node in response to a second signal to decrease a level of current at the output node and a controller reducing an amount of the first and second currents if the first and second currents are generated concurrently. The example method may include supplying a first current to an output node in response to a first signal to increase a level of current at the output node, sinking a second current from the output node in response to a second signal to decrease a level of current at the output node and reducing an amount of the first and second currents if the first and second currents are generated concurrently.

    摘要翻译： 提供一种电荷泵电路及其方法。 示例电荷泵可以包括响应于第一信号向输出节点提供第一电流以提高输出节点处的电流电平的第一开关晶体管，响应于第二开关晶体管从输出节点吸收第二电流 第二信号，用于降低输出节点处的电流电平;以及控制器，如果同时产生第一和第二电流，则减少第一和第二电流的量。 示例性方法可以包括响应于第一信号向输出节点提供第一电流以增加输出节点处的电流电平，响应于第二信号从输出节点吸收第二电流以降低电流电平 并且如果同时产生第一和第二电流，则减少第一和第二电流的量。

    Duty cycle correction circuit, clock generation circuits, semiconductor devices using the same, and method for generating clock signal
    3.
    发明申请
    Duty cycle correction circuit, clock generation circuits, semiconductor devices using the same, and method for generating clock signal 有权
    占空比校正电路，时钟发生电路，使用其的半导体器件，以及用于产生时钟信号的方法

    公开(公告)号：US20070090866A1

    公开(公告)日：2007-04-26

    申请号：US11496447

    申请日：2006-08-01

    申请人： Moon-sook Park ,  Kyu-hyoun Kim

    发明人： Moon-sook Park ,  Kyu-hyoun Kim

    IPC分类号： H03K3/017

    CPC分类号： H03K5/1565 ,  H03K2005/00052 ,  H03L7/08 ,  H03L7/0812 ,  H03L7/0891

    摘要： A semiconductor device and method of generating clock signals where a phase lock loop (PLL), or a delay lock loop (DLL), comprises a duty cycle correction circuit (DCC) having a shared charge pump and a plurality of amplification parts. The plurality of amplification parts generate internal clock signals. The shared charge pump adjusts voltage level of control signal (VC) in response to the internal clock signals and provides the control signal VC to each of the amplification parts.

    摘要翻译： 一种产生时钟信号的半导体器件和方法，其中锁相环（PLL）或延迟锁环（DLL）包括具有共享电荷泵和多个放大部分的占空比校正电路（DCC）。 多个放大部分产生内部时钟信号。 共享电荷泵响应于内部时钟信号调节控制信号（VC）的电压电平，并向每个放大部分提供控制信号VC。

    Input circuit for a memory device, and a memory device and memory system employing the input circuit
    4.
    发明申请
    Input circuit for a memory device, and a memory device and memory system employing the input circuit 有权
    用于存储器件的输入电路，以及采用该输入电路的存储器件和存储器系统

    公开(公告)号：US20070058454A1

    公开(公告)日：2007-03-15

    申请号：US11325343

    申请日：2006-01-05

    申请人： Moon-Sook Park ,  Kyu-hyoun Kim

    发明人： Moon-Sook Park ,  Kyu-hyoun Kim

    IPC分类号： G11C7/10

    CPC分类号： G11C7/1078 ,  G11C7/1084 ,  G11C2207/2254

    摘要： In one embodiment, the input circuit includes a receiver circuit that generates a data signal based on a pair of differential data signals. A detecting circuit detects an offset voltage between the pair of differential data signals, and an adjusting circuit adjusts operation of the receiver to reduce a magnitude of the detected offset voltage based on the detected offset voltage.

    摘要翻译： 在一个实施例中，输入电路包括基于一对差分数据信号产生数据信号的接收器电路。 检测电路检测一对差分数据信号之间的偏移电压，并且调整电路基于检测到的偏移电压来调整接收机的操作以减小检测到的偏移电压的幅度。

    Method of controlling internal voltage and multi-chip package memory prepared using the same
    5.
    发明授权
    Method of controlling internal voltage and multi-chip package memory prepared using the same 有权
    控制内部电压的方法和使用其制备的多芯片封装存储器

    公开(公告)号：US07957217B2

    公开(公告)日：2011-06-07

    申请号：US12266716

    申请日：2008-11-07

    申请人： Moon-sook Park ,  Hoe-ju Chung ,  Jung-bae Lee

    发明人： Moon-sook Park ,  Hoe-ju Chung ,  Jung-bae Lee

    IPC分类号： G11C8/00

    CPC分类号： G11C5/147 ,  G11C5/04

    摘要： The invention relates generally to a multi-chip package (MCP) memory device, and more particularly, but without limitation, to a MCP memory device having a reduced size. In one embodiment, the MCP memory device includes: a transfer memory chip; and a plurality of memory chips coupled to the transfer memory chip, each of the plurality of memory chips including an internal voltage generating circuit, the transfer memory chip configured to receive a plurality of command signals from outside the MCP memory device, the transfer memory chip further configured to output a plurality of control signals to the plurality of memory chips based on the plurality of command signals. Embodiments of the invention also relate to a method of controlling an internal voltage of the MCP memory device.

    摘要翻译： 本发明一般涉及一种多芯片封装（MCP）存储器件，尤其涉及但不限于具有减小尺寸的MCP存储器件。 在一个实施例中，MCP存储器件包括：传送存储器芯片; 以及多个存储器芯片，其耦合到所述传送存储器芯片，所述多个存储器芯片中的每一个包括内部电压产生电路，所述传送存储器芯片被配置为从所述MCP存储器设备的外部接收多个命令信号，所述传送存储器芯片 还被配置为基于所述多个命令信号将多个控制信号输出到所述多个存储器芯片。 本发明的实施例还涉及一种控制MCP存储器件的内部电压的方法。

    Duty cycle correction circuit, clock generation circuits, semiconductor devices using the same, and method for generating clock signal
    6.
    发明授权
    Duty cycle correction circuit, clock generation circuits, semiconductor devices using the same, and method for generating clock signal 有权
    占空比校正电路，时钟发生电路，使用其的半导体器件，以及用于产生时钟信号的方法

    公开(公告)号：US07567106B2

    公开(公告)日：2009-07-28

    申请号：US11496447

    申请日：2006-08-01

    申请人： Moon-sook Park ,  Kyu-hyoun Kim

    发明人： Moon-sook Park ,  Kyu-hyoun Kim

    IPC分类号： H03K3/017

    CPC分类号： H03K5/1565 ,  H03K2005/00052 ,  H03L7/08 ,  H03L7/0812 ,  H03L7/0891

    摘要： A semiconductor device and method of generating clock signals where a phase lock loop (PLL), or a delay lock loop (DLL), comprises a duty cycle correction circuit (DCC) having a shared charge pump and a plurality of amplification parts. The plurality of amplification parts generate internal clock signals. The shared charge pump adjusts voltage level of control signal (VC) in response to the internal clock signals and provides the control signal VC to each of the amplification parts.

    摘要翻译： 一种产生时钟信号的半导体器件和方法，其中锁相环（PLL）或延迟锁环（DLL）包括具有共享电荷泵和多个放大部分的占空比校正电路（DCC）。 多个放大部分产生内部时钟信号。 共享电荷泵响应于内部时钟信号调节控制信号（VC）的电压电平，并向每个放大部分提供控制信号VC。

    DELAY LOCKED LOOP CIRCUITS AND METHODS OF GENERATING CLOCK SIGNALS
    7.
    发明申请
    DELAY LOCKED LOOP CIRCUITS AND METHODS OF GENERATING CLOCK SIGNALS 有权
    延迟锁定环路和产生时钟信号的方法

    公开(公告)号：US20080024180A1

    公开(公告)日：2008-01-31

    申请号：US11761464

    申请日：2007-06-12

    申请人： Moon-Sook PARK ,  Young-Don CHOI

    发明人： Moon-Sook PARK ,  Young-Don CHOI

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0812 ,  H03L7/0891 ,  H03L7/10 ,  H03L7/189

    摘要： A delay locked loop circuit includes a phase detector configured to compare a phase of a reference clock signal with a phase of an output clock signal and to output a comparison signal, a control voltage generator configured to output a control voltage based on the comparison signal, a voltage controlled delay line comprising a plurality of delay elements and configured to delay the reference clock signal based on the control voltage and to output the output clock signal, and a control voltage initializer configured to generate digital codes based on characteristics of the voltage controlled delay line and to generate an initial control voltage based on the digital codes.

    摘要翻译： 延迟锁定环电路包括：相位检测器，被配置为将参考时钟信号的相位与输出时钟信号的相位进行比较并输出比较信号;控制电压发生器，被配置为基于比较信号输出控制电压; 电压控制延迟线，包括多个延迟元件，并且被配置为基于所述控制电压延迟所述参考时钟信号并输出​​所述输出时钟信号;以及控制电压初始化器，被配置为基于所述电压控制延迟的特性生成数字代码 并基于数字代码产生初始控制电压。

    Delay locked loop circuits and methods of generating clock signals
    8.
    发明授权
    Delay locked loop circuits and methods of generating clock signals 有权
    延迟锁定环电路和产生时钟信号的方法

    公开(公告)号：US07622971B2

    公开(公告)日：2009-11-24

    申请号：US11761464

    申请日：2007-06-12

    申请人： Moon-Sook Park ,  Young-Don Choi

    发明人： Moon-Sook Park ,  Young-Don Choi

    IPC分类号： H03L7/00

    CPC分类号： H03L7/0812 ,  H03L7/0891 ,  H03L7/10 ,  H03L7/189

    摘要： A delay locked loop circuit includes a phase detector configured to compare a phase of a reference clock signal with a phase of an output clock signal and to output a comparison signal, a control voltage generator configured to output a control voltage based on the comparison signal, a voltage controlled delay line comprising a plurality of delay elements and configured to delay the reference clock signal based on the control voltage and to output the output clock signal, and a control voltage initializer configured to generate digital codes based on characteristics of the voltage controlled delay line and to generate an initial control voltage based on the digital codes.

    摘要翻译： 延迟锁定环电路包括：相位检测器，被配置为将参考时钟信号的相位与输出时钟信号的相位进行比较并输出比较信号;控制电压发生器，被配置为基于比较信号输出控制电压; 电压控制延迟线，包括多个延迟元件，并且被配置为基于所述控制电压延迟所述参考时钟信号并输出​​所述输出时钟信号;以及控制电压初始化器，被配置为基于所述电压控制延迟的特性来生成数字代码 并基于数字代码产生初始控制电压。

    Phase locked loop circuit and method of locking a phase
    10.
    发明授权
    Phase locked loop circuit and method of locking a phase 有权
    锁相环电路及锁相方法

    公开(公告)号：US07420870B2

    公开(公告)日：2008-09-02

    申请号：US11430199

    申请日：2006-05-09

    申请人： Moon-Sook Park ,  Kyu-Hyoun Kim

    发明人： Moon-Sook Park ,  Kyu-Hyoun Kim

    IPC分类号： G11C8/02 ,  H03L7/06

    CPC分类号： H03L7/0995 ,  H03K3/0315 ,  H03K5/133 ,  H03L7/089 ,  H03L7/0891 ,  H03L7/093

    摘要： A phase locked loop circuit and method of locking a phase. The phased locked loop circuit may include a phase detector receiving an external clock signal and a feedback clock signal and outputting an up signal when a phase of the external clock signal leads a phase of the feedback clock signal and outputting a down signal when the phase of the external clock signal lags the phase of the feedback clock signal, a loop filter circuit increasing a control voltage in response to the up signal and decreasing the control voltage in response to the down signal, and a voltage controlled oscillator circuit receiving the control voltage and directly generating at least n (where n is an integer ≧4) internal clock signals. The phased locked loop circuit may also include a voltage controlled oscillator circuit, including at least four loops, receiving the control voltage and generating multiple internal clock signals.

    摘要翻译： 一种锁相环电路及锁相方法。 相位锁定环电路可以包括接收外部时钟信号和反馈时钟信号的相位检测器，并且当外部时钟信号的相位引导反馈时钟信号的相位并在相位为 外部时钟信号滞后于反馈时钟信号的相位，环路滤波器电路响应于上升信号增加控制电压，并响应于下降信号降低控制电压，以及压控振荡器电路接收控制电压和 直接产生n个（其中n是整数> = 4）内部时钟信号。 相位锁定环路电路还可以包括压控振荡器电路，其包括至少四个环路，接收控制电压并产生多个内部时钟信号。