公开(公告)号：US08395953B2

公开(公告)日：2013-03-12

申请号：US12958726

申请日：2010-12-02

申请人： Cheol Kim ,  Sang-Kyun Park ,  Jung-Bae Lee ,  Jun-Phyo Lee

发明人： Cheol Kim ,  Sang-Kyun Park ,  Jung-Bae Lee ,  Jun-Phyo Lee

IPC分类号： G11C7/00

CPC分类号： G11C11/4091 ,  G11C29/025 ,  G11C29/12005 ,  G11C29/1201 ,  G11C2029/1204

摘要： The bit-line sense amplifier includes a driving-voltage control circuit and an amplifier. The driving-voltage control circuit generates a first test driving voltage having a voltage level of a pre-charge voltage, a second test driving voltage having a voltage level of a pre-charge voltage added by a voltage difference between a bit-line and a complementary bit-line, and a third test driving voltage having a voltage level of a pre-charge voltage subtracted by the voltage difference in a test mode. The amplifier senses and amplifies a voltage difference between the bit-line and the complementary bit-line.

摘要翻译： 位线读出放大器包括驱动电压控制电路和放大器。 驱动电压控制电路产生具有预充电电压的电压电平的第一测试驱动电压，具有由位线和位线之间的电压差相加的预充电电压的电压电平的第二测试驱动电压 以及第三测试驱动电压，其具有在测试模式下被电压差减去的预充电电压的电压电平。 放大器感测并放大位线和互补位线之间的电压差。

公开(公告)号：US08379477B2

公开(公告)日：2013-02-19

申请号：US13019858

申请日：2011-02-02

申请人： Cheol Kim ,  Sang-Kyun Park ,  Jung-Bae Lee ,  Jun-Phyo Lee

发明人： Cheol Kim ,  Sang-Kyun Park ,  Jung-Bae Lee ,  Jun-Phyo Lee

IPC分类号： G11C8/10

CPC分类号： G11C8/14 ,  G11C8/08

摘要： Provided is a semiconductor memory device including a sub-word-line driving circuit capable of reducing an amount of leakage current due to coupling. The semiconductor memory device includes a word-line enable signal generating circuit and a sub-word-line driving circuit. The sub-word-line driving circuit provides a pull-down current path between a selected word line and ground for a pulse type period of time in a precharge mode following an active mode for the selected word line, generates a word line driving signal on the basis of a main word line driving signal, a first sub-word-line control signal, and a second sub-word-line control signal, and provides the word line driving signal to a memory cell array. The semiconductor memory device may reduce an amount of leakage current flowing to a ground through the sub-word-line driving circuit.

摘要翻译： 提供了一种半导体存储器件，其包括能够减少由耦合引起的漏电流量的子字线驱动电路。 半导体存储器件包括字线使能信号发生电路和子字线驱动电路。 子字线驱动电路在所选字线的有效模式之后的预充电模式中的脉冲类型时段期间，在所选字线和地之间提供下拉电流路径，生成字线驱动信号 主字线驱动信号的基础，第一子字线控制信号和第二子字线控制信号，并将字线驱动信号提供给存储单元阵列。 半导体存储器件可以减少通过子字线驱动电路流向地的漏电流量。

公开(公告)号：US20110228624A1

公开(公告)日：2011-09-22

申请号：US13019858

申请日：2011-02-02

申请人： Cheol Kim ,  Sang-Kyun Park ,  Jung-Bae Lee ,  Jun-Phyo Lee

发明人： Cheol Kim ,  Sang-Kyun Park ,  Jung-Bae Lee ,  Jun-Phyo Lee

IPC分类号： G11C8/08

CPC分类号： G11C8/14 ,  G11C8/08

摘要： Provided is a semiconductor memory device including a sub-word-line driving circuit capable of reducing an amount of leakage current due to coupling. The semiconductor memory device includes a word-line enable signal generating circuit and a sub-word-line driving circuit. The sub-word-line driving circuit provides a pull-down current path between a selected word line and ground for a pulse type period of time in a precharge mode following an active mode for the selected word line, generates a word line driving signal on the basis of a main word line driving signal, a first sub-word-line control signal, and a second sub-word-line control signal, and provides the word line driving signal to a memory cell array. The semiconductor memory device may reduce an amount of leakage current flowing to a ground through the sub-word-line driving circuit.

摘要翻译： 提供了一种半导体存储器件，其包括能够减少由耦合引起的漏电流量的子字线驱动电路。 半导体存储器件包括字线使能信号产生电路和子字线驱动电路。 子字线驱动电路在所选字线的有效模式之后的预充电模式中的脉冲类型时段期间，在所选字线和地之间提供下拉电流路径，生成字线驱动信号 主字线驱动信号的基础，第一子字线控制信号和第二子字线控制信号，并将字线驱动信号提供给存储单元阵列。 半导体存储器件可以减少通过子字线驱动电路流向地的漏电流量。

公开(公告)号：US20110199836A1

公开(公告)日：2011-08-18

申请号：US12958726

申请日：2010-12-02

申请人： Cheol Kim ,  Sang-Kyun Park ,  Jung-Bae Lee ,  Jun-Phyo Lee

发明人： Cheol Kim ,  Sang-Kyun Park ,  Jung-Bae Lee ,  Jun-Phyo Lee

IPC分类号： G11C29/12 ,  G11C7/10

CPC分类号： G11C11/4091 ,  G11C29/025 ,  G11C29/12005 ,  G11C29/1201 ,  G11C2029/1204

摘要： The bit-line sense amplifier includes a driving-voltage control circuit and an amplifier. The driving-voltage control circuit generates a first test driving voltage having a voltage level of a pre-charge voltage, a second test driving voltage having a voltage level of a pre-charge voltage added by a voltage difference between a bit-line and a complementary bit-line, and a third test driving voltage having a voltage level of a pre-charge voltage subtracted by the voltage difference in a test mode. The amplifier senses and amplifies a voltage difference between the bit-line and the complementary bit-line.

摘要翻译： 位线读出放大器包括驱动电压控制电路和放大器。 驱动电压控制电路产生具有预充电电压的电压电平的第一测试驱动电压，具有由位线和位线之间的电压差相加的预充电电压的电压电平的第二测试驱动电压 以及第三测试驱动电压，其具有在测试模式下被电压差减去的预充电电压的电压电平。 放大器感测并放大位线和互补位线之间的电压差。

公开(公告)号：US08125846B2

公开(公告)日：2012-02-28

申请号：US12689417

申请日：2010-01-19

申请人： Jun-Phyo Lee

发明人： Jun-Phyo Lee

IPC分类号： G11C5/14

CPC分类号： G11C5/147 ,  G11C5/145

摘要： An internal voltage generating circuit of a semiconductor memory device includes a driving current generator that controls the magnitude of a driving current and supplies a controlled driving current in response to signals activated according to an operational mode. A comparison voltage generator receives a reference voltage and an internal power supply voltage, outputs a differentially amplified comparison voltage in response to a voltage difference between the reference voltage and the internal power supply voltage, and operates according to the driving current. A bulk bias controller receives at least two voltages and selectively outputs a voltage as a bulk bias voltage in response to a power-down enable signal, a normal enable signal, and an operating enable signal. An internal voltage driver controls a threshold voltage in response to the bulk bias voltage, controls a current amount in response to the comparison voltage, and outputs the internal power supply voltage.

摘要翻译： 半导体存储器件的内部电压产生电路包括驱动电流发生器，其控制驱动电流的大小并且响应于根据操作模式激活的信号而提供受控的驱动电流。 比较电压发生器接收参考电压和内部电源电压，响应于参考电压和内部电源电压之间的电压差输出差分放大的比较电压，并根据驱动电流进行工作。 批量偏置控制器接收至少两个电压并且响应于掉电使能信号，正常使能信号和工作使能信号选择性地输出作为体偏置电压的电压。 内部电压驱动器响应于体偏置电压控制阈值电压，响应于比较电压控制电流量，并输出内部电源电压。

公开(公告)号：US20100182867A1

公开(公告)日：2010-07-22

申请号：US12689417

申请日：2010-01-19

申请人： Jun-Phyo Lee

发明人： Jun-Phyo Lee

IPC分类号： G11C5/14

CPC分类号： G11C5/147 ,  G11C5/145

摘要： An internal voltage generating circuit of a semiconductor memory device includes a driving current generator that controls the magnitude of a driving current and supplies a controlled driving current in response to signals activated according to an operational mode. A comparison voltage generator receives a reference voltage and an internal power supply voltage, outputs a differentially amplified comparison voltage in response to a voltage difference between the reference voltage and the internal power supply voltage, and operates according to the driving current. A bulk bias controller receives at least two voltages and selectively outputs a voltage as a bulk bias voltage in response to a power-down enable signal, a normal enable signal, and an operating enable signal. An internal voltage driver controls a threshold voltage in response to the bulk bias voltage, controls a current amount in response to the comparison voltage, and outputs the internal power supply voltage.

摘要翻译： 半导体存储器件的内部电压产生电路包括驱动电流发生器，其控制驱动电流的大小并且响应于根据操作模式激活的信号而提供受控的驱动电流。 比较电压发生器接收参考电压和内部电源电压，响应于参考电压和内部电源电压之间的电压差输出差分放大的比较电压，并根据驱动电流进行工作。 批量偏置控制器接收至少两个电压并且响应于掉电使能信号，正常使能信号和工作使能信号选择性地输出作为体偏置电压的电压。 内部电压驱动器响应于体偏置电压控制阈值电压，响应于比较电压控制电流量，并输出内部电源电压。

公开(公告)号：US07750729B2

公开(公告)日：2010-07-06

申请号：US12071830

申请日：2008-02-27

申请人： Jun-Phyo Lee ,  Young-Gu Kang ,  Beob-Rae Cho

发明人： Jun-Phyo Lee ,  Young-Gu Kang ,  Beob-Rae Cho

IPC分类号： G05F1/10

CPC分类号： G05F1/465 ,  G11C5/147

摘要： An internal voltage generator is disclosed. The internal voltage generator may include a comparator for controlling a voltage of a first node in response to a voltage difference between a reference voltage and an internal voltage, an internal voltage driving portion connected between a driving node and an internal voltage node to apply the internal voltage to the internal voltage node in response to a voltage level of the first node, and/or a leakage current interrupting portion to apply an external voltage to the first node to deactivate the internal voltage driving portion and to interrupt the external voltage applied to the driving node to interrupt a leakage current.

摘要翻译： 公开了内部电压发生器。 内部电压发生器可以包括用于响应于参考电压和内部电压之间的电压差来控制第一节点的电压的比较器，连接在驱动节点和内部电压节点之间的内部电压驱动部分以应用内部电压 响应于第一节点的电压电平到内部电压节点的电压和/或泄漏电流中断部分，以向第一节点施加外部电压以去激活内部电压驱动部分并且中断施加到第一节点的外部电压 驱动节点中断漏电流。

公开(公告)号：US20080204125A1

公开(公告)日：2008-08-28

申请号：US12071830

申请日：2008-02-27

申请人： Jun-Phyo Lee ,  Young-Gu Kang ,  Beob-Rae Cho

发明人： Jun-Phyo Lee ,  Young-Gu Kang ,  Beob-Rae Cho

IPC分类号： G05F1/10

CPC分类号： G05F1/465 ,  G11C5/147

摘要： An internal voltage generator is disclosed. The internal voltage generator may include a comparator for controlling a voltage of a first node in response to a voltage difference between a reference voltage and an internal voltage, an internal voltage driving portion connected between a driving node and an internal voltage node to apply the internal voltage to the internal voltage node in response to a voltage level of the first node, and/or a leakage current interrupting portion to apply an external voltage to the first node to deactivate the internal voltage driving portion and to interrupt the external voltage applied to the driving node to interrupt a leakage current.

摘要翻译： 公开了内部电压发生器。 内部电压发生器可以包括用于响应于参考电压和内部电压之间的电压差来控制第一节点的电压的比较器，连接在驱动节点和内部电压节点之间的内部电压驱动部分以应用内部电压 响应于第一节点的电压电平到内部电压节点的电压和/或泄漏电流中断部分，以向第一节点施加外部电压以停用内部电压驱动部分并且中断施加到第一节点的外部电压 驱动节点中断漏电流。